tests/output/ex1_3.out

3   Processor [0] M 4 N 4 m 2 n 2 w 1 s 1
5   Processor [1] M 4 N 4 m 2 n 2 w 1 s 1
7   Processor [2] M 4 N 4 m 2 n 2 w 1 s 1
9   Processor [3] M 4 N 4 m 2 n 2 w 1 s 1
11 Patch 0: (0, 0, 0)--(2, 2, 1)
12 Processor [0] M 3 N 3 m 2 n 2 w 1 s 0
14 Processor [1] M 3 N 3 m 2 n 2 w 1 s 0
16 Processor [2] M 3 N 3 m 2 n 2 w 1 s 0
18 Processor [3] M 3 N 3 m 2 n 2 w 1 s 0
23   [0] 0 <- (0,0)
24   [0] 1 <- (0,1)
25   [0] 2 <- (0,2)
26   [0] 3 <- (0,3)
28   [1] 0 <- (1,0)
29   [1] 1 <- (1,2)
31   [2] 0 <- (2,0)
32   [2] 1 <- (2,1)
34   [3] 0 <- (3,0)
38   [0] 0 <- (0,0)
39   [0] 1 <- (0,1)
40   [0] 3 <- (0,2)
41   [0] 4 <- (0,3)
45 Patch 1: (2, 0, 0)--(4, 2, 1)
46 Processor [0] M 3 N 3 m 2 n 2 w 1 s 0
48 Processor [1] M 3 N 3 m 2 n 2 w 1 s 0
50 Processor [2] M 3 N 3 m 2 n 2 w 1 s 0
52 Processor [3] M 3 N 3 m 2 n 2 w 1 s 0
57   [0] 0 <- (0,1)
58   [0] 1 <- (1,0)
59   [0] 2 <- (0,3)
60   [0] 3 <- (1,2)
62   [1] 0 <- (1,1)
63   [1] 1 <- (1,3)
65   [2] 0 <- (2,1)
66   [2] 1 <- (3,0)
68   [3] 0 <- (3,1)
72   [0] 1 <- (1,0)
73   [0] 4 <- (1,2)
75   [1] 0 <- (1,1)
76   [1] 3 <- (1,3)
79 Patch 2: (0, 2, 0)--(2, 4, 1)
80 Processor [0] M 3 N 3 m 2 n 2 w 1 s 0
82 Processor [1] M 3 N 3 m 2 n 2 w 1 s 0
84 Processor [2] M 3 N 3 m 2 n 2 w 1 s 0
86 Processor [3] M 3 N 3 m 2 n 2 w 1 s 0
91   [0] 0 <- (0,2)
92   [0] 1 <- (0,3)
93   [0] 2 <- (2,0)
94   [0] 3 <- (2,1)
96   [1] 0 <- (1,2)
97   [1] 1 <- (3,0)
99   [2] 0 <- (2,2)
100   [2] 1 <- (2,3)
102   [3] 0 <- (3,2)
106   [0] 3 <- (2,0)
107   [0] 4 <- (2,1)
110   [2] 0 <- (2,2)
111   [2] 1 <- (2,3)
113 Patch 3: (2, 2, 0)--(4, 4, 1)
114 Processor [0] M 3 N 3 m 2 n 2 w 1 s 0
116 Processor [1] M 3 N 3 m 2 n 2 w 1 s 0
118 Processor [2] M 3 N 3 m 2 n 2 w 1 s 0
120 Processor [3] M 3 N 3 m 2 n 2 w 1 s 0
125   [0] 0 <- (0,3)
126   [0] 1 <- (1,2)
127   [0] 2 <- (2,1)
128   [0] 3 <- (3,0)
130   [1] 0 <- (1,3)
131   [1] 1 <- (3,1)
133   [2] 0 <- (2,3)
134   [2] 1 <- (3,2)
136   [3] 0 <- (3,3)
140   [0] 4 <- (3,0)
142   [1] 3 <- (3,1)
144   [2] 1 <- (3,2)
146   [3] 0 <- (3,3)