1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip designware mobile storage host controller 8 9description: 10 Rockchip uses the Synopsys designware mobile storage host controller 11 to interface a SoC with storage medium such as eMMC or SD/MMC cards. 12 This file documents the combined properties for the core Synopsys dw mshc 13 controller that are not already included in the synopsys-dw-mshc-common.yaml 14 file and the Rockchip specific extensions. 15 16allOf: 17 - $ref: synopsys-dw-mshc-common.yaml# 18 19maintainers: 20 - Heiko Stuebner <heiko@sntech.de> 21 22# Everything else is described in the common file 23properties: 24 compatible: 25 oneOf: 26 # for Rockchip RK2928 and before RK3288 27 - const: rockchip,rk2928-dw-mshc 28 # for Rockchip RK3288 29 - const: rockchip,rk3288-dw-mshc 30 - items: 31 - enum: 32 - rockchip,px30-dw-mshc 33 - rockchip,rk1808-dw-mshc 34 - rockchip,rk3036-dw-mshc 35 - rockchip,rk3128-dw-mshc 36 - rockchip,rk3228-dw-mshc 37 - rockchip,rk3308-dw-mshc 38 - rockchip,rk3328-dw-mshc 39 - rockchip,rk3368-dw-mshc 40 - rockchip,rk3399-dw-mshc 41 - rockchip,rk3506-dw-mshc 42 - rockchip,rk3528-dw-mshc 43 - rockchip,rk3562-dw-mshc 44 - rockchip,rk3568-dw-mshc 45 - rockchip,rk3588-dw-mshc 46 - rockchip,rv1108-dw-mshc 47 - rockchip,rv1126-dw-mshc 48 - const: rockchip,rk3288-dw-mshc 49 # for Rockchip RK3576 with phase tuning inside the controller 50 - items: 51 - enum: 52 - rockchip,rv1103b-dw-mshc 53 - const: rockchip,rk3576-dw-mshc 54 - const: rockchip,rk3576-dw-mshc 55 56 reg: 57 maxItems: 1 58 59 interrupts: 60 maxItems: 1 61 62 clocks: 63 minItems: 2 64 maxItems: 4 65 description: 66 Handle to "biu" and "ciu" clocks for the bus interface unit clock and 67 the card interface unit clock. If "ciu-drive" and "ciu-sample" are 68 specified in clock-names, it should also contain 69 handles to these clocks. 70 71 clock-names: 72 minItems: 2 73 items: 74 - const: biu 75 - const: ciu 76 - const: ciu-drive 77 - const: ciu-sample 78 description: 79 Apart from the clock-names "biu" and "ciu" two more clocks 80 "ciu-drive" and "ciu-sample" are supported. They are used 81 to control the clock phases, "ciu-sample" is required for tuning 82 high speed modes. 83 84 power-domains: 85 maxItems: 1 86 87 rockchip,default-sample-phase: 88 $ref: /schemas/types.yaml#/definitions/uint32 89 minimum: 0 90 maximum: 360 91 default: 0 92 description: 93 The default phase to set "ciu-sample" at probing, 94 low speeds or in case where all phases work at tuning time. 95 If not specified 0 deg will be used. 96 97 rockchip,desired-num-phases: 98 $ref: /schemas/types.yaml#/definitions/uint32 99 minimum: 0 100 maximum: 360 101 default: 360 102 description: 103 The desired number of times that the host execute tuning when needed. 104 If not specified, the host will do tuning for 360 times, 105 namely tuning for each degree. 106 107required: 108 - compatible 109 - reg 110 - interrupts 111 - clocks 112 - clock-names 113 114unevaluatedProperties: false 115 116examples: 117 - | 118 #include <dt-bindings/clock/rk3288-cru.h> 119 #include <dt-bindings/interrupt-controller/arm-gic.h> 120 #include <dt-bindings/interrupt-controller/irq.h> 121 sdmmc: mmc@ff0c0000 { 122 compatible = "rockchip,rk3288-dw-mshc"; 123 reg = <0xff0c0000 0x4000>; 124 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 126 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 127 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 128 resets = <&cru SRST_MMC0>; 129 reset-names = "reset"; 130 fifo-depth = <0x100>; 131 max-frequency = <150000000>; 132 }; 133 134... 135