1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for I2C adapter in Rockchip RK3xxx SoC
4 *
5 * Max Schwarz <max.schwarz@online.de>
6 * based on the patches by Rockchip Inc.
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/i2c.h>
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/errno.h>
15 #include <linux/err.h>
16 #include <linux/platform_device.h>
17 #include <linux/io.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/spinlock.h>
21 #include <linux/clk.h>
22 #include <linux/units.h>
23 #include <linux/wait.h>
24 #include <linux/mfd/syscon.h>
25 #include <linux/regmap.h>
26 #include <linux/math64.h>
27
28
29 /* Register Map */
30 #define REG_CON 0x00 /* control register */
31 #define REG_CLKDIV 0x04 /* clock divisor register */
32 #define REG_MRXADDR 0x08 /* target address for REGISTER_TX */
33 #define REG_MRXRADDR 0x0c /* target register address for REGISTER_TX */
34 #define REG_MTXCNT 0x10 /* number of bytes to be transmitted */
35 #define REG_MRXCNT 0x14 /* number of bytes to be received */
36 #define REG_IEN 0x18 /* interrupt enable */
37 #define REG_IPD 0x1c /* interrupt pending */
38 #define REG_FCNT 0x20 /* finished count */
39
40 /* Data buffer offsets */
41 #define TXBUFFER_BASE 0x100
42 #define RXBUFFER_BASE 0x200
43
44 /* REG_CON bits */
45 #define REG_CON_EN BIT(0)
46 enum {
47 REG_CON_MOD_TX = 0, /* transmit data */
48 REG_CON_MOD_REGISTER_TX, /* select register and restart */
49 REG_CON_MOD_RX, /* receive data */
50 REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes
51 * register addr */
52 };
53 #define REG_CON_MOD(mod) ((mod) << 1)
54 #define REG_CON_MOD_MASK (BIT(1) | BIT(2))
55 #define REG_CON_START BIT(3)
56 #define REG_CON_STOP BIT(4)
57 #define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */
58 #define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */
59
60 #define REG_CON_TUNING_MASK GENMASK_ULL(15, 8)
61
62 #define REG_CON_SDA_CFG(cfg) ((cfg) << 8)
63 #define REG_CON_STA_CFG(cfg) ((cfg) << 12)
64 #define REG_CON_STO_CFG(cfg) ((cfg) << 14)
65
66 /* REG_MRXADDR bits */
67 #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */
68
69 /* REG_IEN/REG_IPD bits */
70 #define REG_INT_BTF BIT(0) /* a byte was transmitted */
71 #define REG_INT_BRF BIT(1) /* a byte was received */
72 #define REG_INT_MBTF BIT(2) /* controller data transmit finished */
73 #define REG_INT_MBRF BIT(3) /* controller data receive finished */
74 #define REG_INT_START BIT(4) /* START condition generated */
75 #define REG_INT_STOP BIT(5) /* STOP condition generated */
76 #define REG_INT_NAKRCV BIT(6) /* NACK received */
77 #define REG_INT_ALL 0x7f
78
79 /* Constants */
80 #define WAIT_TIMEOUT 1000 /* ms */
81 #define DEFAULT_SCL_RATE (100 * 1000) /* Hz */
82
83 /**
84 * struct i2c_spec_values - I2C specification values for various modes
85 * @min_hold_start_ns: min hold time (repeated) START condition
86 * @min_low_ns: min LOW period of the SCL clock
87 * @min_high_ns: min HIGH period of the SCL cloc
88 * @min_setup_start_ns: min set-up time for a repeated START conditio
89 * @max_data_hold_ns: max data hold time
90 * @min_data_setup_ns: min data set-up time
91 * @min_setup_stop_ns: min set-up time for STOP condition
92 * @min_hold_buffer_ns: min bus free time between a STOP and
93 * START condition
94 */
95 struct i2c_spec_values {
96 unsigned long min_hold_start_ns;
97 unsigned long min_low_ns;
98 unsigned long min_high_ns;
99 unsigned long min_setup_start_ns;
100 unsigned long max_data_hold_ns;
101 unsigned long min_data_setup_ns;
102 unsigned long min_setup_stop_ns;
103 unsigned long min_hold_buffer_ns;
104 };
105
106 static const struct i2c_spec_values standard_mode_spec = {
107 .min_hold_start_ns = 4000,
108 .min_low_ns = 4700,
109 .min_high_ns = 4000,
110 .min_setup_start_ns = 4700,
111 .max_data_hold_ns = 3450,
112 .min_data_setup_ns = 250,
113 .min_setup_stop_ns = 4000,
114 .min_hold_buffer_ns = 4700,
115 };
116
117 static const struct i2c_spec_values fast_mode_spec = {
118 .min_hold_start_ns = 600,
119 .min_low_ns = 1300,
120 .min_high_ns = 600,
121 .min_setup_start_ns = 600,
122 .max_data_hold_ns = 900,
123 .min_data_setup_ns = 100,
124 .min_setup_stop_ns = 600,
125 .min_hold_buffer_ns = 1300,
126 };
127
128 static const struct i2c_spec_values fast_mode_plus_spec = {
129 .min_hold_start_ns = 260,
130 .min_low_ns = 500,
131 .min_high_ns = 260,
132 .min_setup_start_ns = 260,
133 .max_data_hold_ns = 400,
134 .min_data_setup_ns = 50,
135 .min_setup_stop_ns = 260,
136 .min_hold_buffer_ns = 500,
137 };
138
139 /**
140 * struct rk3x_i2c_calced_timings - calculated V1 timings
141 * @div_low: Divider output for low
142 * @div_high: Divider output for high
143 * @tuning: Used to adjust setup/hold data time,
144 * setup/hold start time and setup stop time for
145 * v1's calc_timings, the tuning should all be 0
146 * for old hardware anyone using v0's calc_timings.
147 */
148 struct rk3x_i2c_calced_timings {
149 unsigned long div_low;
150 unsigned long div_high;
151 unsigned int tuning;
152 };
153
154 enum rk3x_i2c_state {
155 STATE_IDLE,
156 STATE_START,
157 STATE_READ,
158 STATE_WRITE,
159 STATE_STOP
160 };
161
162 /**
163 * struct rk3x_i2c_soc_data - SOC-specific data
164 * @grf_offset: offset inside the grf regmap for setting the i2c type
165 * @calc_timings: Callback function for i2c timing information calculated
166 */
167 struct rk3x_i2c_soc_data {
168 int grf_offset;
169 int (*calc_timings)(unsigned long, struct i2c_timings *,
170 struct rk3x_i2c_calced_timings *);
171 };
172
173 /**
174 * struct rk3x_i2c - private data of the controller
175 * @adap: corresponding I2C adapter
176 * @dev: device for this controller
177 * @soc_data: related soc data struct
178 * @regs: virtual memory area
179 * @clk: function clk for rk3399 or function & Bus clks for others
180 * @pclk: Bus clk for rk3399
181 * @clk_rate_nb: i2c clk rate change notify
182 * @irq: irq number
183 * @t: I2C known timing information
184 * @lock: spinlock for the i2c bus
185 * @wait: the waitqueue to wait for i2c transfer
186 * @busy: the condition for the event to wait for
187 * @msg: current i2c message
188 * @addr: addr of i2c target device
189 * @mode: mode of i2c transfer
190 * @is_last_msg: flag determines whether it is the last msg in this transfer
191 * @state: state of i2c transfer
192 * @processed: byte length which has been send or received
193 * @error: error code for i2c transfer
194 */
195 struct rk3x_i2c {
196 struct i2c_adapter adap;
197 struct device *dev;
198 const struct rk3x_i2c_soc_data *soc_data;
199
200 /* Hardware resources */
201 void __iomem *regs;
202 struct clk *clk;
203 struct clk *pclk;
204 struct notifier_block clk_rate_nb;
205 int irq;
206
207 /* Settings */
208 struct i2c_timings t;
209
210 /* Synchronization & notification */
211 spinlock_t lock;
212 wait_queue_head_t wait;
213 bool busy;
214
215 /* Current message */
216 struct i2c_msg *msg;
217 u8 addr;
218 unsigned int mode;
219 bool is_last_msg;
220
221 /* I2C state machine */
222 enum rk3x_i2c_state state;
223 unsigned int processed;
224 int error;
225 };
226
i2c_writel(struct rk3x_i2c * i2c,u32 value,unsigned int offset)227 static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value,
228 unsigned int offset)
229 {
230 writel(value, i2c->regs + offset);
231 }
232
i2c_readl(struct rk3x_i2c * i2c,unsigned int offset)233 static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset)
234 {
235 return readl(i2c->regs + offset);
236 }
237
238 /* Reset all interrupt pending bits */
rk3x_i2c_clean_ipd(struct rk3x_i2c * i2c)239 static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c)
240 {
241 i2c_writel(i2c, REG_INT_ALL, REG_IPD);
242 }
243
244 /**
245 * rk3x_i2c_start - Generate a START condition, which triggers a REG_INT_START interrupt.
246 * @i2c: target controller data
247 */
rk3x_i2c_start(struct rk3x_i2c * i2c)248 static void rk3x_i2c_start(struct rk3x_i2c *i2c)
249 {
250 u32 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
251
252 i2c_writel(i2c, REG_INT_START, REG_IEN);
253
254 /* enable adapter with correct mode, send START condition */
255 val |= REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START;
256
257 /* if we want to react to NACK, set ACTACK bit */
258 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
259 val |= REG_CON_ACTACK;
260
261 i2c_writel(i2c, val, REG_CON);
262 }
263
264 /**
265 * rk3x_i2c_stop - Generate a STOP condition, which triggers a REG_INT_STOP interrupt.
266 * @i2c: target controller data
267 * @error: Error code to return in rk3x_i2c_xfer
268 */
rk3x_i2c_stop(struct rk3x_i2c * i2c,int error)269 static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error)
270 {
271 unsigned int ctrl;
272
273 i2c->processed = 0;
274 i2c->msg = NULL;
275 i2c->error = error;
276
277 if (i2c->is_last_msg) {
278 /* Enable stop interrupt */
279 i2c_writel(i2c, REG_INT_STOP, REG_IEN);
280
281 i2c->state = STATE_STOP;
282
283 ctrl = i2c_readl(i2c, REG_CON);
284 ctrl |= REG_CON_STOP;
285 i2c_writel(i2c, ctrl, REG_CON);
286 } else {
287 /* Signal rk3x_i2c_xfer to start the next message. */
288 i2c->busy = false;
289 i2c->state = STATE_IDLE;
290
291 /*
292 * The HW is actually not capable of REPEATED START. But we can
293 * get the intended effect by resetting its internal state
294 * and issuing an ordinary START.
295 */
296 ctrl = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
297 i2c_writel(i2c, ctrl, REG_CON);
298
299 /* signal that we are finished with the current msg */
300 wake_up(&i2c->wait);
301 }
302 }
303
304 /**
305 * rk3x_i2c_prepare_read - Setup a read according to i2c->msg
306 * @i2c: target controller data
307 */
rk3x_i2c_prepare_read(struct rk3x_i2c * i2c)308 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c)
309 {
310 unsigned int len = i2c->msg->len - i2c->processed;
311 u32 con;
312
313 con = i2c_readl(i2c, REG_CON);
314
315 /*
316 * The hw can read up to 32 bytes at a time. If we need more than one
317 * chunk, send an ACK after the last byte of the current chunk.
318 */
319 if (len > 32) {
320 len = 32;
321 con &= ~REG_CON_LASTACK;
322 } else {
323 con |= REG_CON_LASTACK;
324 }
325
326 /* make sure we are in plain RX mode if we read a second chunk */
327 if (i2c->processed != 0) {
328 con &= ~REG_CON_MOD_MASK;
329 con |= REG_CON_MOD(REG_CON_MOD_RX);
330 }
331
332 i2c_writel(i2c, con, REG_CON);
333 i2c_writel(i2c, len, REG_MRXCNT);
334 }
335
336 /**
337 * rk3x_i2c_fill_transmit_buf - Fill the transmit buffer with data from i2c->msg
338 * @i2c: target controller data
339 */
rk3x_i2c_fill_transmit_buf(struct rk3x_i2c * i2c)340 static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c)
341 {
342 unsigned int i, j;
343 u32 cnt = 0;
344 u32 val;
345 u8 byte;
346
347 for (i = 0; i < 8; ++i) {
348 val = 0;
349 for (j = 0; j < 4; ++j) {
350 if ((i2c->processed == i2c->msg->len) && (cnt != 0))
351 break;
352
353 if (i2c->processed == 0 && cnt == 0)
354 byte = (i2c->addr & 0x7f) << 1;
355 else
356 byte = i2c->msg->buf[i2c->processed++];
357
358 val |= byte << (j * 8);
359 cnt++;
360 }
361
362 i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i);
363
364 if (i2c->processed == i2c->msg->len)
365 break;
366 }
367
368 i2c_writel(i2c, cnt, REG_MTXCNT);
369 }
370
371
372 /* IRQ handlers for individual states */
373
rk3x_i2c_handle_start(struct rk3x_i2c * i2c,unsigned int ipd)374 static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd)
375 {
376 if (!(ipd & REG_INT_START)) {
377 rk3x_i2c_stop(i2c, -EIO);
378 dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd);
379 rk3x_i2c_clean_ipd(i2c);
380 return;
381 }
382
383 /* ack interrupt */
384 i2c_writel(i2c, REG_INT_START, REG_IPD);
385
386 /* disable start bit */
387 i2c_writel(i2c, i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON);
388
389 /* enable appropriate interrupts and transition */
390 if (i2c->mode == REG_CON_MOD_TX) {
391 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN);
392 i2c->state = STATE_WRITE;
393 rk3x_i2c_fill_transmit_buf(i2c);
394 } else {
395 /* in any other case, we are going to be reading. */
396 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN);
397 i2c->state = STATE_READ;
398 rk3x_i2c_prepare_read(i2c);
399 }
400 }
401
rk3x_i2c_handle_write(struct rk3x_i2c * i2c,unsigned int ipd)402 static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd)
403 {
404 if (!(ipd & REG_INT_MBTF)) {
405 rk3x_i2c_stop(i2c, -EIO);
406 dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd);
407 rk3x_i2c_clean_ipd(i2c);
408 return;
409 }
410
411 /* ack interrupt */
412 i2c_writel(i2c, REG_INT_MBTF, REG_IPD);
413
414 /* are we finished? */
415 if (i2c->processed == i2c->msg->len)
416 rk3x_i2c_stop(i2c, i2c->error);
417 else
418 rk3x_i2c_fill_transmit_buf(i2c);
419 }
420
rk3x_i2c_handle_read(struct rk3x_i2c * i2c,unsigned int ipd)421 static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd)
422 {
423 unsigned int i;
424 unsigned int len = i2c->msg->len - i2c->processed;
425 u32 val;
426 u8 byte;
427
428 /* we only care for MBRF here. */
429 if (!(ipd & REG_INT_MBRF))
430 return;
431
432 /* ack interrupt (read also produces a spurious START flag, clear it too) */
433 i2c_writel(i2c, REG_INT_MBRF | REG_INT_START, REG_IPD);
434
435 /* Can only handle a maximum of 32 bytes at a time */
436 if (len > 32)
437 len = 32;
438
439 /* read the data from receive buffer */
440 for (i = 0; i < len; ++i) {
441 if (i % 4 == 0)
442 val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4);
443
444 byte = (val >> ((i % 4) * 8)) & 0xff;
445 i2c->msg->buf[i2c->processed++] = byte;
446 }
447
448 /* are we finished? */
449 if (i2c->processed == i2c->msg->len)
450 rk3x_i2c_stop(i2c, i2c->error);
451 else
452 rk3x_i2c_prepare_read(i2c);
453 }
454
rk3x_i2c_handle_stop(struct rk3x_i2c * i2c,unsigned int ipd)455 static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd)
456 {
457 unsigned int con;
458
459 if (!(ipd & REG_INT_STOP)) {
460 rk3x_i2c_stop(i2c, -EIO);
461 dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd);
462 rk3x_i2c_clean_ipd(i2c);
463 return;
464 }
465
466 /* ack interrupt */
467 i2c_writel(i2c, REG_INT_STOP, REG_IPD);
468
469 /* disable STOP bit */
470 con = i2c_readl(i2c, REG_CON);
471 con &= ~REG_CON_STOP;
472 i2c_writel(i2c, con, REG_CON);
473
474 i2c->busy = false;
475 i2c->state = STATE_IDLE;
476
477 /* signal rk3x_i2c_xfer that we are finished */
478 wake_up(&i2c->wait);
479 }
480
rk3x_i2c_irq(int irqno,void * dev_id)481 static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id)
482 {
483 struct rk3x_i2c *i2c = dev_id;
484 unsigned int ipd;
485
486 spin_lock(&i2c->lock);
487
488 ipd = i2c_readl(i2c, REG_IPD);
489 if (i2c->state == STATE_IDLE) {
490 dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd);
491 rk3x_i2c_clean_ipd(i2c);
492 goto out;
493 }
494
495 dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd);
496
497 /* Clean interrupt bits we don't care about */
498 ipd &= ~(REG_INT_BRF | REG_INT_BTF);
499
500 if (ipd & REG_INT_NAKRCV) {
501 /*
502 * We got a NACK in the last operation. Depending on whether
503 * IGNORE_NAK is set, we have to stop the operation and report
504 * an error.
505 */
506 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD);
507
508 ipd &= ~REG_INT_NAKRCV;
509
510 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
511 rk3x_i2c_stop(i2c, -ENXIO);
512 }
513
514 /* is there anything left to handle? */
515 if ((ipd & REG_INT_ALL) == 0)
516 goto out;
517
518 switch (i2c->state) {
519 case STATE_START:
520 rk3x_i2c_handle_start(i2c, ipd);
521 break;
522 case STATE_WRITE:
523 rk3x_i2c_handle_write(i2c, ipd);
524 break;
525 case STATE_READ:
526 rk3x_i2c_handle_read(i2c, ipd);
527 break;
528 case STATE_STOP:
529 rk3x_i2c_handle_stop(i2c, ipd);
530 break;
531 case STATE_IDLE:
532 break;
533 }
534
535 out:
536 spin_unlock(&i2c->lock);
537 return IRQ_HANDLED;
538 }
539
540 /**
541 * rk3x_i2c_get_spec - Get timing values of I2C specification
542 * @speed: Desired SCL frequency
543 *
544 * Return: Matched i2c_spec_values.
545 */
rk3x_i2c_get_spec(unsigned int speed)546 static const struct i2c_spec_values *rk3x_i2c_get_spec(unsigned int speed)
547 {
548 if (speed <= I2C_MAX_STANDARD_MODE_FREQ)
549 return &standard_mode_spec;
550 else if (speed <= I2C_MAX_FAST_MODE_FREQ)
551 return &fast_mode_spec;
552 else
553 return &fast_mode_plus_spec;
554 }
555
556 /**
557 * rk3x_i2c_v0_calc_timings - Calculate divider values for desired SCL frequency
558 * @clk_rate: I2C input clock rate
559 * @t: Known I2C timing information
560 * @t_calc: Caculated rk3x private timings that would be written into regs
561 *
562 * Return: %0 on success, -%EINVAL if the goal SCL rate is too slow. In that case
563 * a best-effort divider value is returned in divs. If the target rate is
564 * too high, we silently use the highest possible rate.
565 */
rk3x_i2c_v0_calc_timings(unsigned long clk_rate,struct i2c_timings * t,struct rk3x_i2c_calced_timings * t_calc)566 static int rk3x_i2c_v0_calc_timings(unsigned long clk_rate,
567 struct i2c_timings *t,
568 struct rk3x_i2c_calced_timings *t_calc)
569 {
570 unsigned long min_low_ns, min_high_ns;
571 unsigned long max_low_ns, min_total_ns;
572
573 unsigned long clk_rate_khz, scl_rate_khz;
574
575 unsigned long min_low_div, min_high_div;
576 unsigned long max_low_div;
577
578 unsigned long min_div_for_hold, min_total_div;
579 unsigned long extra_div, extra_low_div, ideal_low_div;
580
581 unsigned long data_hold_buffer_ns = 50;
582 const struct i2c_spec_values *spec;
583 int ret = 0;
584
585 /* Only support standard-mode and fast-mode */
586 if (WARN_ON(t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ))
587 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
588
589 /* prevent scl_rate_khz from becoming 0 */
590 if (WARN_ON(t->bus_freq_hz < 1000))
591 t->bus_freq_hz = 1000;
592
593 /*
594 * min_low_ns: The minimum number of ns we need to hold low to
595 * meet I2C specification, should include fall time.
596 * min_high_ns: The minimum number of ns we need to hold high to
597 * meet I2C specification, should include rise time.
598 * max_low_ns: The maximum number of ns we can hold low to meet
599 * I2C specification.
600 *
601 * Note: max_low_ns should be (maximum data hold time * 2 - buffer)
602 * This is because the i2c host on Rockchip holds the data line
603 * for half the low time.
604 */
605 spec = rk3x_i2c_get_spec(t->bus_freq_hz);
606 min_high_ns = t->scl_rise_ns + spec->min_high_ns;
607
608 /*
609 * Timings for repeated start:
610 * - controller appears to drop SDA at .875x (7/8) programmed clk high.
611 * - controller appears to keep SCL high for 2x programmed clk high.
612 *
613 * We need to account for those rules in picking our "high" time so
614 * we meet tSU;STA and tHD;STA times.
615 */
616 min_high_ns = max(min_high_ns, DIV_ROUND_UP(
617 (t->scl_rise_ns + spec->min_setup_start_ns) * 1000, 875));
618 min_high_ns = max(min_high_ns, DIV_ROUND_UP(
619 (t->scl_rise_ns + spec->min_setup_start_ns + t->sda_fall_ns +
620 spec->min_high_ns), 2));
621
622 min_low_ns = t->scl_fall_ns + spec->min_low_ns;
623 max_low_ns = spec->max_data_hold_ns * 2 - data_hold_buffer_ns;
624 min_total_ns = min_low_ns + min_high_ns;
625
626 /* Adjust to avoid overflow */
627 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
628 scl_rate_khz = t->bus_freq_hz / 1000;
629
630 /*
631 * We need the total div to be >= this number
632 * so we don't clock too fast.
633 */
634 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
635
636 /* These are the min dividers needed for min hold times. */
637 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
638 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
639 min_div_for_hold = (min_low_div + min_high_div);
640
641 /*
642 * This is the maximum divider so we don't go over the maximum.
643 * We don't round up here (we round down) since this is a maximum.
644 */
645 max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000);
646
647 if (min_low_div > max_low_div) {
648 WARN_ONCE(true,
649 "Conflicting, min_low_div %lu, max_low_div %lu\n",
650 min_low_div, max_low_div);
651 max_low_div = min_low_div;
652 }
653
654 if (min_div_for_hold > min_total_div) {
655 /*
656 * Time needed to meet hold requirements is important.
657 * Just use that.
658 */
659 t_calc->div_low = min_low_div;
660 t_calc->div_high = min_high_div;
661 } else {
662 /*
663 * We've got to distribute some time among the low and high
664 * so we don't run too fast.
665 */
666 extra_div = min_total_div - min_div_for_hold;
667
668 /*
669 * We'll try to split things up perfectly evenly,
670 * biasing slightly towards having a higher div
671 * for low (spend more time low).
672 */
673 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns,
674 scl_rate_khz * 8 * min_total_ns);
675
676 /* Don't allow it to go over the maximum */
677 if (ideal_low_div > max_low_div)
678 ideal_low_div = max_low_div;
679
680 /*
681 * Handle when the ideal low div is going to take up
682 * more than we have.
683 */
684 if (ideal_low_div > min_low_div + extra_div)
685 ideal_low_div = min_low_div + extra_div;
686
687 /* Give low the "ideal" and give high whatever extra is left */
688 extra_low_div = ideal_low_div - min_low_div;
689 t_calc->div_low = ideal_low_div;
690 t_calc->div_high = min_high_div + (extra_div - extra_low_div);
691 }
692
693 /*
694 * Adjust to the fact that the hardware has an implicit "+1".
695 * NOTE: Above calculations always produce div_low > 0 and div_high > 0.
696 */
697 t_calc->div_low--;
698 t_calc->div_high--;
699
700 /* Give the tuning value 0, that would not update con register */
701 t_calc->tuning = 0;
702 /* Maximum divider supported by hw is 0xffff */
703 if (t_calc->div_low > 0xffff) {
704 t_calc->div_low = 0xffff;
705 ret = -EINVAL;
706 }
707
708 if (t_calc->div_high > 0xffff) {
709 t_calc->div_high = 0xffff;
710 ret = -EINVAL;
711 }
712
713 return ret;
714 }
715
716 /**
717 * rk3x_i2c_v1_calc_timings - Calculate timing values for desired SCL frequency
718 * @clk_rate: I2C input clock rate
719 * @t: Known I2C timing information
720 * @t_calc: Caculated rk3x private timings that would be written into regs
721 *
722 * Return: %0 on success, -%EINVAL if the goal SCL rate is too slow. In that case
723 * a best-effort divider value is returned in divs. If the target rate is
724 * too high, we silently use the highest possible rate.
725 * The following formulas are v1's method to calculate timings.
726 *
727 * l = divl + 1;
728 * h = divh + 1;
729 * s = sda_update_config + 1;
730 * u = start_setup_config + 1;
731 * p = stop_setup_config + 1;
732 * T = Tclk_i2c;
733 *
734 * tHigh = 8 * h * T;
735 * tLow = 8 * l * T;
736 *
737 * tHD;sda = (l * s + 1) * T;
738 * tSU;sda = [(8 - s) * l + 1] * T;
739 * tI2C = 8 * (l + h) * T;
740 *
741 * tSU;sta = (8h * u + 1) * T;
742 * tHD;sta = [8h * (u + 1) - 1] * T;
743 * tSU;sto = (8h * p + 1) * T;
744 */
rk3x_i2c_v1_calc_timings(unsigned long clk_rate,struct i2c_timings * t,struct rk3x_i2c_calced_timings * t_calc)745 static int rk3x_i2c_v1_calc_timings(unsigned long clk_rate,
746 struct i2c_timings *t,
747 struct rk3x_i2c_calced_timings *t_calc)
748 {
749 unsigned long min_low_ns, min_high_ns;
750 unsigned long min_setup_start_ns, min_setup_data_ns;
751 unsigned long min_setup_stop_ns, max_hold_data_ns;
752
753 unsigned long clk_rate_khz, scl_rate_khz;
754
755 unsigned long min_low_div, min_high_div;
756
757 unsigned long min_div_for_hold, min_total_div;
758 unsigned long extra_div, extra_low_div;
759 unsigned long sda_update_cfg, stp_sta_cfg, stp_sto_cfg;
760
761 const struct i2c_spec_values *spec;
762 int ret = 0;
763
764 /* Support standard-mode, fast-mode and fast-mode plus */
765 if (WARN_ON(t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ))
766 t->bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ;
767
768 /* prevent scl_rate_khz from becoming 0 */
769 if (WARN_ON(t->bus_freq_hz < 1000))
770 t->bus_freq_hz = 1000;
771
772 /*
773 * min_low_ns: The minimum number of ns we need to hold low to
774 * meet I2C specification, should include fall time.
775 * min_high_ns: The minimum number of ns we need to hold high to
776 * meet I2C specification, should include rise time.
777 */
778 spec = rk3x_i2c_get_spec(t->bus_freq_hz);
779
780 /* calculate min-divh and min-divl */
781 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
782 scl_rate_khz = t->bus_freq_hz / 1000;
783 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
784
785 min_high_ns = t->scl_rise_ns + spec->min_high_ns;
786 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
787
788 min_low_ns = t->scl_fall_ns + spec->min_low_ns;
789 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
790
791 /*
792 * Final divh and divl must be greater than 0, otherwise the
793 * hardware would not output the i2c clk.
794 */
795 min_high_div = (min_high_div < 1) ? 2 : min_high_div;
796 min_low_div = (min_low_div < 1) ? 2 : min_low_div;
797
798 /* These are the min dividers needed for min hold times. */
799 min_div_for_hold = (min_low_div + min_high_div);
800
801 /*
802 * This is the maximum divider so we don't go over the maximum.
803 * We don't round up here (we round down) since this is a maximum.
804 */
805 if (min_div_for_hold >= min_total_div) {
806 /*
807 * Time needed to meet hold requirements is important.
808 * Just use that.
809 */
810 t_calc->div_low = min_low_div;
811 t_calc->div_high = min_high_div;
812 } else {
813 /*
814 * We've got to distribute some time among the low and high
815 * so we don't run too fast.
816 * We'll try to split things up by the scale of min_low_div and
817 * min_high_div, biasing slightly towards having a higher div
818 * for low (spend more time low).
819 */
820 extra_div = min_total_div - min_div_for_hold;
821 extra_low_div = DIV_ROUND_UP(min_low_div * extra_div,
822 min_div_for_hold);
823
824 t_calc->div_low = min_low_div + extra_low_div;
825 t_calc->div_high = min_high_div + (extra_div - extra_low_div);
826 }
827
828 /*
829 * calculate sda data hold count by the rules, data_upd_st:3
830 * is a appropriate value to reduce calculated times.
831 */
832 for (sda_update_cfg = 3; sda_update_cfg > 0; sda_update_cfg--) {
833 max_hold_data_ns = DIV_ROUND_UP((sda_update_cfg
834 * (t_calc->div_low) + 1)
835 * 1000000, clk_rate_khz);
836 min_setup_data_ns = DIV_ROUND_UP(((8 - sda_update_cfg)
837 * (t_calc->div_low) + 1)
838 * 1000000, clk_rate_khz);
839 if ((max_hold_data_ns < spec->max_data_hold_ns) &&
840 (min_setup_data_ns > spec->min_data_setup_ns))
841 break;
842 }
843
844 /* calculate setup start config */
845 min_setup_start_ns = t->scl_rise_ns + spec->min_setup_start_ns;
846 stp_sta_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_start_ns
847 - 1000000, 8 * 1000000 * (t_calc->div_high));
848
849 /* calculate setup stop config */
850 min_setup_stop_ns = t->scl_rise_ns + spec->min_setup_stop_ns;
851 stp_sto_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_stop_ns
852 - 1000000, 8 * 1000000 * (t_calc->div_high));
853
854 t_calc->tuning = REG_CON_SDA_CFG(--sda_update_cfg) |
855 REG_CON_STA_CFG(--stp_sta_cfg) |
856 REG_CON_STO_CFG(--stp_sto_cfg);
857
858 t_calc->div_low--;
859 t_calc->div_high--;
860
861 /* Maximum divider supported by hw is 0xffff */
862 if (t_calc->div_low > 0xffff) {
863 t_calc->div_low = 0xffff;
864 ret = -EINVAL;
865 }
866
867 if (t_calc->div_high > 0xffff) {
868 t_calc->div_high = 0xffff;
869 ret = -EINVAL;
870 }
871
872 return ret;
873 }
874
rk3x_i2c_adapt_div(struct rk3x_i2c * i2c,unsigned long clk_rate)875 static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
876 {
877 struct i2c_timings *t = &i2c->t;
878 struct rk3x_i2c_calced_timings calc;
879 u64 t_low_ns, t_high_ns;
880 unsigned long flags;
881 u32 val;
882 int ret;
883
884 ret = i2c->soc_data->calc_timings(clk_rate, t, &calc);
885 WARN_ONCE(ret != 0, "Could not reach SCL freq %u", t->bus_freq_hz);
886
887 clk_enable(i2c->pclk);
888
889 spin_lock_irqsave(&i2c->lock, flags);
890 val = i2c_readl(i2c, REG_CON);
891 val &= ~REG_CON_TUNING_MASK;
892 val |= calc.tuning;
893 i2c_writel(i2c, val, REG_CON);
894 i2c_writel(i2c, (calc.div_high << 16) | (calc.div_low & 0xffff),
895 REG_CLKDIV);
896 spin_unlock_irqrestore(&i2c->lock, flags);
897
898 clk_disable(i2c->pclk);
899
900 t_low_ns = div_u64(8ULL * HZ_PER_GHZ * (calc.div_low + 1), clk_rate);
901 t_high_ns = div_u64(8ULL * HZ_PER_GHZ * (calc.div_high + 1), clk_rate);
902 dev_dbg(i2c->dev,
903 "CLK %lukHz, Req %luns, Act low %lluns high %lluns\n",
904 clk_rate / HZ_PER_KHZ,
905 HZ_PER_GHZ / t->bus_freq_hz,
906 t_low_ns, t_high_ns);
907 }
908
909 /**
910 * rk3x_i2c_clk_notifier_cb - Clock rate change callback
911 * @nb: Pointer to notifier block
912 * @event: Notification reason
913 * @data: Pointer to notification data object
914 *
915 * The callback checks whether a valid bus frequency can be generated after the
916 * change. If so, the change is acknowledged, otherwise the change is aborted.
917 * New dividers are written to the HW in the pre- or post change notification
918 * depending on the scaling direction.
919 *
920 * Code adapted from i2c-cadence.c.
921 *
922 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
923 * to acknowledge the change, NOTIFY_DONE if the notification is
924 * considered irrelevant.
925 */
rk3x_i2c_clk_notifier_cb(struct notifier_block * nb,unsigned long event,void * data)926 static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
927 event, void *data)
928 {
929 struct clk_notifier_data *ndata = data;
930 struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb);
931 struct rk3x_i2c_calced_timings calc;
932
933 switch (event) {
934 case PRE_RATE_CHANGE:
935 /*
936 * Try the calculation (but don't store the result) ahead of
937 * time to see if we need to block the clock change. Timings
938 * shouldn't actually take effect until rk3x_i2c_adapt_div().
939 */
940 if (i2c->soc_data->calc_timings(ndata->new_rate, &i2c->t,
941 &calc) != 0)
942 return NOTIFY_STOP;
943
944 /* scale up */
945 if (ndata->new_rate > ndata->old_rate)
946 rk3x_i2c_adapt_div(i2c, ndata->new_rate);
947
948 return NOTIFY_OK;
949 case POST_RATE_CHANGE:
950 /* scale down */
951 if (ndata->new_rate < ndata->old_rate)
952 rk3x_i2c_adapt_div(i2c, ndata->new_rate);
953 return NOTIFY_OK;
954 case ABORT_RATE_CHANGE:
955 /* scale up */
956 if (ndata->new_rate > ndata->old_rate)
957 rk3x_i2c_adapt_div(i2c, ndata->old_rate);
958 return NOTIFY_OK;
959 default:
960 return NOTIFY_DONE;
961 }
962 }
963
964 /**
965 * rk3x_i2c_setup - Setup I2C registers for an I2C operation specified by msgs, num.
966 * @i2c: target controller data
967 * @msgs: I2C msgs to process
968 * @num: Number of msgs
969 *
970 * Must be called with i2c->lock held.
971 *
972 * Return: Number of I2C msgs processed or negative in case of error
973 */
rk3x_i2c_setup(struct rk3x_i2c * i2c,struct i2c_msg * msgs,int num)974 static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num)
975 {
976 u32 addr = (msgs[0].addr & 0x7f) << 1;
977 int ret = 0;
978
979 /*
980 * The I2C adapter can issue a small (len < 4) write packet before
981 * reading. This speeds up SMBus-style register reads.
982 * The MRXADDR/MRXRADDR hold the target address and the target register
983 * address in this case.
984 */
985
986 if (num >= 2 && msgs[0].len < 4 &&
987 !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
988 u32 reg_addr = 0;
989 int i;
990
991 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n",
992 addr >> 1);
993
994 /* Fill MRXRADDR with the register address(es) */
995 for (i = 0; i < msgs[0].len; ++i) {
996 reg_addr |= msgs[0].buf[i] << (i * 8);
997 reg_addr |= REG_MRXADDR_VALID(i);
998 }
999
1000 /* msgs[0] is handled by hw. */
1001 i2c->msg = &msgs[1];
1002
1003 i2c->mode = REG_CON_MOD_REGISTER_TX;
1004
1005 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR);
1006 i2c_writel(i2c, reg_addr, REG_MRXRADDR);
1007
1008 ret = 2;
1009 } else {
1010 /*
1011 * We'll have to do it the boring way and process the msgs
1012 * one-by-one.
1013 */
1014
1015 if (msgs[0].flags & I2C_M_RD) {
1016 addr |= 1; /* set read bit */
1017
1018 /*
1019 * We have to transmit the target addr first. Use
1020 * MOD_REGISTER_TX for that purpose.
1021 */
1022 i2c->mode = REG_CON_MOD_REGISTER_TX;
1023 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0),
1024 REG_MRXADDR);
1025 i2c_writel(i2c, 0, REG_MRXRADDR);
1026 } else {
1027 i2c->mode = REG_CON_MOD_TX;
1028 }
1029
1030 i2c->msg = &msgs[0];
1031
1032 ret = 1;
1033 }
1034
1035 i2c->addr = msgs[0].addr;
1036 i2c->busy = true;
1037 i2c->state = STATE_START;
1038 i2c->processed = 0;
1039 i2c->error = 0;
1040
1041 rk3x_i2c_clean_ipd(i2c);
1042
1043 return ret;
1044 }
1045
rk3x_i2c_wait_xfer_poll(struct rk3x_i2c * i2c)1046 static int rk3x_i2c_wait_xfer_poll(struct rk3x_i2c *i2c)
1047 {
1048 ktime_t timeout = ktime_add_ms(ktime_get(), WAIT_TIMEOUT);
1049
1050 while (READ_ONCE(i2c->busy) &&
1051 ktime_compare(ktime_get(), timeout) < 0) {
1052 udelay(5);
1053 rk3x_i2c_irq(0, i2c);
1054 }
1055
1056 return !i2c->busy;
1057 }
1058
rk3x_i2c_xfer_common(struct i2c_adapter * adap,struct i2c_msg * msgs,int num,bool polling)1059 static int rk3x_i2c_xfer_common(struct i2c_adapter *adap,
1060 struct i2c_msg *msgs, int num, bool polling)
1061 {
1062 struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data;
1063 unsigned long flags;
1064 long time_left;
1065 u32 val;
1066 int ret = 0;
1067 int i;
1068
1069 spin_lock_irqsave(&i2c->lock, flags);
1070
1071 clk_enable(i2c->clk);
1072 clk_enable(i2c->pclk);
1073
1074 i2c->is_last_msg = false;
1075
1076 /*
1077 * Process msgs. We can handle more than one message at once (see
1078 * rk3x_i2c_setup()).
1079 */
1080 for (i = 0; i < num; i += ret) {
1081 ret = rk3x_i2c_setup(i2c, msgs + i, num - i);
1082
1083 if (ret < 0) {
1084 dev_err(i2c->dev, "rk3x_i2c_setup() failed\n");
1085 break;
1086 }
1087
1088 if (i + ret >= num)
1089 i2c->is_last_msg = true;
1090
1091 spin_unlock_irqrestore(&i2c->lock, flags);
1092
1093 if (!polling) {
1094 rk3x_i2c_start(i2c);
1095
1096 time_left = wait_event_timeout(i2c->wait, !i2c->busy,
1097 msecs_to_jiffies(WAIT_TIMEOUT));
1098 } else {
1099 disable_irq(i2c->irq);
1100 rk3x_i2c_start(i2c);
1101
1102 time_left = rk3x_i2c_wait_xfer_poll(i2c);
1103
1104 enable_irq(i2c->irq);
1105 }
1106
1107 spin_lock_irqsave(&i2c->lock, flags);
1108
1109 if (time_left == 0) {
1110 /* Force a STOP condition without interrupt */
1111 i2c_writel(i2c, 0, REG_IEN);
1112 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
1113 val |= REG_CON_EN | REG_CON_STOP;
1114 i2c_writel(i2c, val, REG_CON);
1115
1116 i2c->state = STATE_IDLE;
1117
1118 ret = -ETIMEDOUT;
1119 break;
1120 }
1121
1122 if (i2c->error) {
1123 ret = i2c->error;
1124 break;
1125 }
1126 }
1127
1128 clk_disable(i2c->pclk);
1129 clk_disable(i2c->clk);
1130
1131 spin_unlock_irqrestore(&i2c->lock, flags);
1132
1133 return ret < 0 ? ret : num;
1134 }
1135
rk3x_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)1136 static int rk3x_i2c_xfer(struct i2c_adapter *adap,
1137 struct i2c_msg *msgs, int num)
1138 {
1139 return rk3x_i2c_xfer_common(adap, msgs, num, false);
1140 }
1141
rk3x_i2c_xfer_polling(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)1142 static int rk3x_i2c_xfer_polling(struct i2c_adapter *adap,
1143 struct i2c_msg *msgs, int num)
1144 {
1145 return rk3x_i2c_xfer_common(adap, msgs, num, true);
1146 }
1147
rk3x_i2c_resume(struct device * dev)1148 static __maybe_unused int rk3x_i2c_resume(struct device *dev)
1149 {
1150 struct rk3x_i2c *i2c = dev_get_drvdata(dev);
1151
1152 rk3x_i2c_adapt_div(i2c, clk_get_rate(i2c->clk));
1153
1154 return 0;
1155 }
1156
rk3x_i2c_func(struct i2c_adapter * adap)1157 static u32 rk3x_i2c_func(struct i2c_adapter *adap)
1158 {
1159 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
1160 }
1161
1162 static const struct i2c_algorithm rk3x_i2c_algorithm = {
1163 .xfer = rk3x_i2c_xfer,
1164 .xfer_atomic = rk3x_i2c_xfer_polling,
1165 .functionality = rk3x_i2c_func,
1166 };
1167
1168 static const struct rk3x_i2c_soc_data rv1108_soc_data = {
1169 .grf_offset = -1,
1170 .calc_timings = rk3x_i2c_v1_calc_timings,
1171 };
1172
1173 static const struct rk3x_i2c_soc_data rv1126_soc_data = {
1174 .grf_offset = 0x118,
1175 .calc_timings = rk3x_i2c_v1_calc_timings,
1176 };
1177
1178 static const struct rk3x_i2c_soc_data rk3066_soc_data = {
1179 .grf_offset = 0x154,
1180 .calc_timings = rk3x_i2c_v0_calc_timings,
1181 };
1182
1183 static const struct rk3x_i2c_soc_data rk3188_soc_data = {
1184 .grf_offset = 0x0a4,
1185 .calc_timings = rk3x_i2c_v0_calc_timings,
1186 };
1187
1188 static const struct rk3x_i2c_soc_data rk3228_soc_data = {
1189 .grf_offset = -1,
1190 .calc_timings = rk3x_i2c_v0_calc_timings,
1191 };
1192
1193 static const struct rk3x_i2c_soc_data rk3288_soc_data = {
1194 .grf_offset = -1,
1195 .calc_timings = rk3x_i2c_v0_calc_timings,
1196 };
1197
1198 static const struct rk3x_i2c_soc_data rk3399_soc_data = {
1199 .grf_offset = -1,
1200 .calc_timings = rk3x_i2c_v1_calc_timings,
1201 };
1202
1203 static const struct of_device_id rk3x_i2c_match[] = {
1204 {
1205 .compatible = "rockchip,rv1108-i2c",
1206 .data = &rv1108_soc_data
1207 },
1208 {
1209 .compatible = "rockchip,rv1126-i2c",
1210 .data = &rv1126_soc_data
1211 },
1212 {
1213 .compatible = "rockchip,rk3066-i2c",
1214 .data = &rk3066_soc_data
1215 },
1216 {
1217 .compatible = "rockchip,rk3188-i2c",
1218 .data = &rk3188_soc_data
1219 },
1220 {
1221 .compatible = "rockchip,rk3228-i2c",
1222 .data = &rk3228_soc_data
1223 },
1224 {
1225 .compatible = "rockchip,rk3288-i2c",
1226 .data = &rk3288_soc_data
1227 },
1228 {
1229 .compatible = "rockchip,rk3399-i2c",
1230 .data = &rk3399_soc_data
1231 },
1232 {},
1233 };
1234 MODULE_DEVICE_TABLE(of, rk3x_i2c_match);
1235
rk3x_i2c_probe(struct platform_device * pdev)1236 static int rk3x_i2c_probe(struct platform_device *pdev)
1237 {
1238 struct device_node *np = pdev->dev.of_node;
1239 const struct of_device_id *match;
1240 struct rk3x_i2c *i2c;
1241 int ret = 0;
1242 int bus_nr;
1243 u32 value;
1244 int irq;
1245 unsigned long clk_rate;
1246
1247 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL);
1248 if (!i2c)
1249 return -ENOMEM;
1250
1251 match = of_match_node(rk3x_i2c_match, np);
1252 i2c->soc_data = match->data;
1253
1254 /* use common interface to get I2C timing properties */
1255 i2c_parse_fw_timings(&pdev->dev, &i2c->t, true);
1256
1257 strscpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
1258 i2c->adap.owner = THIS_MODULE;
1259 i2c->adap.algo = &rk3x_i2c_algorithm;
1260 i2c->adap.retries = 3;
1261 i2c->adap.dev.of_node = np;
1262 i2c->adap.algo_data = i2c;
1263 i2c->adap.dev.parent = &pdev->dev;
1264
1265 i2c->dev = &pdev->dev;
1266
1267 spin_lock_init(&i2c->lock);
1268 init_waitqueue_head(&i2c->wait);
1269
1270 i2c->regs = devm_platform_ioremap_resource(pdev, 0);
1271 if (IS_ERR(i2c->regs))
1272 return PTR_ERR(i2c->regs);
1273
1274 /* Try to set the I2C adapter number from dt */
1275 bus_nr = of_alias_get_id(np, "i2c");
1276
1277 /*
1278 * Switch to new interface if the SoC also offers the old one.
1279 * The control bit is located in the GRF register space.
1280 */
1281 if (i2c->soc_data->grf_offset >= 0) {
1282 struct regmap *grf;
1283
1284 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1285 if (IS_ERR(grf)) {
1286 dev_err(&pdev->dev,
1287 "rk3x-i2c needs 'rockchip,grf' property\n");
1288 return PTR_ERR(grf);
1289 }
1290
1291 if (bus_nr < 0) {
1292 dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias");
1293 return -EINVAL;
1294 }
1295
1296 /* rv1126 i2c2 uses non-sequential write mask 20, value 4 */
1297 if (i2c->soc_data == &rv1126_soc_data && bus_nr == 2)
1298 value = BIT(20) | BIT(4);
1299 else
1300 /* 27+i: write mask, 11+i: value */
1301 value = BIT(27 + bus_nr) | BIT(11 + bus_nr);
1302
1303 ret = regmap_write(grf, i2c->soc_data->grf_offset, value);
1304 if (ret != 0) {
1305 dev_err(i2c->dev, "Could not write to GRF: %d\n", ret);
1306 return ret;
1307 }
1308 }
1309
1310 /* IRQ setup */
1311 irq = platform_get_irq(pdev, 0);
1312 if (irq < 0)
1313 return irq;
1314
1315 ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq,
1316 0, dev_name(&pdev->dev), i2c);
1317 if (ret < 0) {
1318 dev_err(&pdev->dev, "cannot request IRQ\n");
1319 return ret;
1320 }
1321
1322 i2c->irq = irq;
1323
1324 platform_set_drvdata(pdev, i2c);
1325
1326 if (i2c->soc_data->calc_timings == rk3x_i2c_v0_calc_timings) {
1327 /* Only one clock to use for bus clock and peripheral clock */
1328 i2c->clk = devm_clk_get(&pdev->dev, NULL);
1329 i2c->pclk = i2c->clk;
1330 } else {
1331 i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1332 i2c->pclk = devm_clk_get(&pdev->dev, "pclk");
1333 }
1334
1335 if (IS_ERR(i2c->clk))
1336 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk),
1337 "Can't get bus clk\n");
1338
1339 if (IS_ERR(i2c->pclk))
1340 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->pclk),
1341 "Can't get periph clk\n");
1342
1343 ret = clk_prepare(i2c->clk);
1344 if (ret < 0) {
1345 dev_err(&pdev->dev, "Can't prepare bus clk: %d\n", ret);
1346 return ret;
1347 }
1348 ret = clk_prepare(i2c->pclk);
1349 if (ret < 0) {
1350 dev_err(&pdev->dev, "Can't prepare periph clock: %d\n", ret);
1351 goto err_clk;
1352 }
1353
1354 i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb;
1355 ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb);
1356 if (ret != 0) {
1357 dev_err(&pdev->dev, "Unable to register clock notifier\n");
1358 goto err_pclk;
1359 }
1360
1361 ret = clk_enable(i2c->clk);
1362 if (ret < 0) {
1363 dev_err(&pdev->dev, "Can't enable bus clk: %d\n", ret);
1364 goto err_clk_notifier;
1365 }
1366
1367 clk_rate = clk_get_rate(i2c->clk);
1368 rk3x_i2c_adapt_div(i2c, clk_rate);
1369 clk_disable(i2c->clk);
1370
1371 ret = i2c_add_adapter(&i2c->adap);
1372 if (ret < 0)
1373 goto err_clk_notifier;
1374
1375 return 0;
1376
1377 err_clk_notifier:
1378 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1379 err_pclk:
1380 clk_unprepare(i2c->pclk);
1381 err_clk:
1382 clk_unprepare(i2c->clk);
1383 return ret;
1384 }
1385
rk3x_i2c_remove(struct platform_device * pdev)1386 static void rk3x_i2c_remove(struct platform_device *pdev)
1387 {
1388 struct rk3x_i2c *i2c = platform_get_drvdata(pdev);
1389
1390 i2c_del_adapter(&i2c->adap);
1391
1392 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1393 clk_unprepare(i2c->pclk);
1394 clk_unprepare(i2c->clk);
1395 }
1396
1397 static SIMPLE_DEV_PM_OPS(rk3x_i2c_pm_ops, NULL, rk3x_i2c_resume);
1398
1399 static struct platform_driver rk3x_i2c_driver = {
1400 .probe = rk3x_i2c_probe,
1401 .remove = rk3x_i2c_remove,
1402 .driver = {
1403 .name = "rk3x-i2c",
1404 .of_match_table = rk3x_i2c_match,
1405 .pm = &rk3x_i2c_pm_ops,
1406 },
1407 };
1408
1409 module_platform_driver(rk3x_i2c_driver);
1410
1411 MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver");
1412 MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>");
1413 MODULE_LICENSE("GPL v2");
1414