1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 STMicroelectronics
4 *
5 * I2C controller driver, used in STMicroelectronics devices.
6 *
7 * Author: Maxime Coquelin <maxime.coquelin@st.com>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/err.h>
13 #include <linux/i2c.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/minmax.h>
17 #include <linux/module.h>
18 #include <linux/of_address.h>
19 #include <linux/of_irq.h>
20 #include <linux/of.h>
21 #include <linux/pinctrl/consumer.h>
22 #include <linux/platform_device.h>
23 #include <linux/units.h>
24
25 /* SSC registers */
26 #define SSC_BRG 0x000
27 #define SSC_TBUF 0x004
28 #define SSC_RBUF 0x008
29 #define SSC_CTL 0x00C
30 #define SSC_IEN 0x010
31 #define SSC_STA 0x014
32 #define SSC_I2C 0x018
33 #define SSC_SLAD 0x01C
34 #define SSC_REP_START_HOLD 0x020
35 #define SSC_START_HOLD 0x024
36 #define SSC_REP_START_SETUP 0x028
37 #define SSC_DATA_SETUP 0x02C
38 #define SSC_STOP_SETUP 0x030
39 #define SSC_BUS_FREE 0x034
40 #define SSC_TX_FSTAT 0x038
41 #define SSC_RX_FSTAT 0x03C
42 #define SSC_PRE_SCALER_BRG 0x040
43 #define SSC_CLR 0x080
44 #define SSC_NOISE_SUPP_WIDTH 0x100
45 #define SSC_PRSCALER 0x104
46 #define SSC_NOISE_SUPP_WIDTH_DATAOUT 0x108
47 #define SSC_PRSCALER_DATAOUT 0x10c
48
49 /* SSC Control */
50 #define SSC_CTL_DATA_WIDTH_9 0x8
51 #define SSC_CTL_DATA_WIDTH_MSK 0xf
52 #define SSC_CTL_BM 0xf
53 #define SSC_CTL_HB BIT(4)
54 #define SSC_CTL_PH BIT(5)
55 #define SSC_CTL_PO BIT(6)
56 #define SSC_CTL_SR BIT(7)
57 #define SSC_CTL_MS BIT(8)
58 #define SSC_CTL_EN BIT(9)
59 #define SSC_CTL_LPB BIT(10)
60 #define SSC_CTL_EN_TX_FIFO BIT(11)
61 #define SSC_CTL_EN_RX_FIFO BIT(12)
62 #define SSC_CTL_EN_CLST_RX BIT(13)
63
64 /* SSC Interrupt Enable */
65 #define SSC_IEN_RIEN BIT(0)
66 #define SSC_IEN_TIEN BIT(1)
67 #define SSC_IEN_TEEN BIT(2)
68 #define SSC_IEN_REEN BIT(3)
69 #define SSC_IEN_PEEN BIT(4)
70 #define SSC_IEN_AASEN BIT(6)
71 #define SSC_IEN_STOPEN BIT(7)
72 #define SSC_IEN_ARBLEN BIT(8)
73 #define SSC_IEN_NACKEN BIT(10)
74 #define SSC_IEN_REPSTRTEN BIT(11)
75 #define SSC_IEN_TX_FIFO_HALF BIT(12)
76 #define SSC_IEN_RX_FIFO_HALF_FULL BIT(14)
77
78 /* SSC Status */
79 #define SSC_STA_RIR BIT(0)
80 #define SSC_STA_TIR BIT(1)
81 #define SSC_STA_TE BIT(2)
82 #define SSC_STA_RE BIT(3)
83 #define SSC_STA_PE BIT(4)
84 #define SSC_STA_CLST BIT(5)
85 #define SSC_STA_AAS BIT(6)
86 #define SSC_STA_STOP BIT(7)
87 #define SSC_STA_ARBL BIT(8)
88 #define SSC_STA_BUSY BIT(9)
89 #define SSC_STA_NACK BIT(10)
90 #define SSC_STA_REPSTRT BIT(11)
91 #define SSC_STA_TX_FIFO_HALF BIT(12)
92 #define SSC_STA_TX_FIFO_FULL BIT(13)
93 #define SSC_STA_RX_FIFO_HALF BIT(14)
94
95 /* SSC I2C Control */
96 #define SSC_I2C_I2CM BIT(0)
97 #define SSC_I2C_STRTG BIT(1)
98 #define SSC_I2C_STOPG BIT(2)
99 #define SSC_I2C_ACKG BIT(3)
100 #define SSC_I2C_AD10 BIT(4)
101 #define SSC_I2C_TXENB BIT(5)
102 #define SSC_I2C_REPSTRTG BIT(11)
103 #define SSC_I2C_SLAVE_DISABLE BIT(12)
104
105 /* SSC Tx FIFO Status */
106 #define SSC_TX_FSTAT_STATUS 0x07
107
108 /* SSC Rx FIFO Status */
109 #define SSC_RX_FSTAT_STATUS 0x07
110
111 /* SSC Clear bit operation */
112 #define SSC_CLR_SSCAAS BIT(6)
113 #define SSC_CLR_SSCSTOP BIT(7)
114 #define SSC_CLR_SSCARBL BIT(8)
115 #define SSC_CLR_NACK BIT(10)
116 #define SSC_CLR_REPSTRT BIT(11)
117
118 /* SSC Clock Prescaler */
119 #define SSC_PRSC_VALUE 0x0f
120
121
122 #define SSC_TXFIFO_SIZE 0x8
123 #define SSC_RXFIFO_SIZE 0x8
124
125 enum st_i2c_mode {
126 I2C_MODE_STANDARD,
127 I2C_MODE_FAST,
128 I2C_MODE_END,
129 };
130
131 /**
132 * struct st_i2c_timings - per-Mode tuning parameters
133 * @rate: I2C bus rate
134 * @rep_start_hold: I2C repeated start hold time requirement
135 * @rep_start_setup: I2C repeated start set up time requirement
136 * @start_hold: I2C start hold time requirement
137 * @data_setup_time: I2C data set up time requirement
138 * @stop_setup_time: I2C stop set up time requirement
139 * @bus_free_time: I2C bus free time requirement
140 * @sda_pulse_min_limit: I2C SDA pulse mini width limit
141 */
142 struct st_i2c_timings {
143 u32 rate;
144 u32 rep_start_hold;
145 u32 rep_start_setup;
146 u32 start_hold;
147 u32 data_setup_time;
148 u32 stop_setup_time;
149 u32 bus_free_time;
150 u32 sda_pulse_min_limit;
151 };
152
153 /**
154 * struct st_i2c_client - client specific data
155 * @addr: 8-bit target addr, including r/w bit
156 * @count: number of bytes to be transferred
157 * @xfered: number of bytes already transferred
158 * @buf: data buffer
159 * @result: result of the transfer
160 * @stop: last I2C msg to be sent, i.e. STOP to be generated
161 */
162 struct st_i2c_client {
163 u8 addr;
164 u32 count;
165 u32 xfered;
166 u8 *buf;
167 int result;
168 bool stop;
169 };
170
171 /**
172 * struct st_i2c_dev - private data of the controller
173 * @adap: I2C adapter for this controller
174 * @dev: device for this controller
175 * @base: virtual memory area
176 * @complete: completion of I2C message
177 * @irq: interrupt line for th controller
178 * @clk: hw ssc block clock
179 * @mode: I2C mode of the controller. Standard or Fast only supported
180 * @scl_min_width_us: SCL line minimum pulse width in us
181 * @sda_min_width_us: SDA line minimum pulse width in us
182 * @client: I2C transfert information
183 * @busy: I2C transfer on-going
184 */
185 struct st_i2c_dev {
186 struct i2c_adapter adap;
187 struct device *dev;
188 void __iomem *base;
189 struct completion complete;
190 int irq;
191 struct clk *clk;
192 int mode;
193 u32 scl_min_width_us;
194 u32 sda_min_width_us;
195 struct st_i2c_client client;
196 bool busy;
197 };
198
st_i2c_set_bits(void __iomem * reg,u32 mask)199 static inline void st_i2c_set_bits(void __iomem *reg, u32 mask)
200 {
201 writel_relaxed(readl_relaxed(reg) | mask, reg);
202 }
203
st_i2c_clr_bits(void __iomem * reg,u32 mask)204 static inline void st_i2c_clr_bits(void __iomem *reg, u32 mask)
205 {
206 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
207 }
208
209 /*
210 * From I2C Specifications v0.5.
211 *
212 * All the values below have +10% margin added to be
213 * compatible with some out-of-spec devices,
214 * like HDMI link of the Toshiba 19AV600 TV.
215 */
216 static struct st_i2c_timings i2c_timings[] = {
217 [I2C_MODE_STANDARD] = {
218 .rate = I2C_MAX_STANDARD_MODE_FREQ,
219 .rep_start_hold = 4400,
220 .rep_start_setup = 5170,
221 .start_hold = 4400,
222 .data_setup_time = 275,
223 .stop_setup_time = 4400,
224 .bus_free_time = 5170,
225 },
226 [I2C_MODE_FAST] = {
227 .rate = I2C_MAX_FAST_MODE_FREQ,
228 .rep_start_hold = 660,
229 .rep_start_setup = 660,
230 .start_hold = 660,
231 .data_setup_time = 110,
232 .stop_setup_time = 660,
233 .bus_free_time = 1430,
234 },
235 };
236
st_i2c_flush_rx_fifo(struct st_i2c_dev * i2c_dev)237 static void st_i2c_flush_rx_fifo(struct st_i2c_dev *i2c_dev)
238 {
239 int count, i;
240
241 /*
242 * Counter only counts up to 7 but fifo size is 8...
243 * When fifo is full, counter is 0 and RIR bit of status register is
244 * set
245 */
246 if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR)
247 count = SSC_RXFIFO_SIZE;
248 else
249 count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) &
250 SSC_RX_FSTAT_STATUS;
251
252 for (i = 0; i < count; i++)
253 readl_relaxed(i2c_dev->base + SSC_RBUF);
254 }
255
st_i2c_soft_reset(struct st_i2c_dev * i2c_dev)256 static void st_i2c_soft_reset(struct st_i2c_dev *i2c_dev)
257 {
258 /*
259 * FIFO needs to be emptied before reseting the IP,
260 * else the controller raises a BUSY error.
261 */
262 st_i2c_flush_rx_fifo(i2c_dev);
263
264 st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR);
265 st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR);
266 }
267
268 /**
269 * st_i2c_hw_config() - Prepare SSC block, calculate and apply tuning timings
270 * @i2c_dev: Controller's private data
271 */
st_i2c_hw_config(struct st_i2c_dev * i2c_dev)272 static void st_i2c_hw_config(struct st_i2c_dev *i2c_dev)
273 {
274 unsigned long rate;
275 u32 val, ns_per_clk;
276 struct st_i2c_timings *t = &i2c_timings[i2c_dev->mode];
277
278 st_i2c_soft_reset(i2c_dev);
279
280 val = SSC_CLR_REPSTRT | SSC_CLR_NACK | SSC_CLR_SSCARBL |
281 SSC_CLR_SSCAAS | SSC_CLR_SSCSTOP;
282 writel_relaxed(val, i2c_dev->base + SSC_CLR);
283
284 /* SSC Control register setup */
285 val = SSC_CTL_PO | SSC_CTL_PH | SSC_CTL_HB | SSC_CTL_DATA_WIDTH_9;
286 writel_relaxed(val, i2c_dev->base + SSC_CTL);
287
288 rate = clk_get_rate(i2c_dev->clk);
289 ns_per_clk = HZ_PER_GHZ / rate;
290
291 /* Baudrate */
292 val = rate / (2 * t->rate);
293 writel_relaxed(val, i2c_dev->base + SSC_BRG);
294
295 /* Pre-scaler baudrate */
296 writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG);
297
298 /* Enable I2C mode */
299 writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C);
300
301 /* Repeated start hold time */
302 val = t->rep_start_hold / ns_per_clk;
303 writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD);
304
305 /* Repeated start set up time */
306 val = t->rep_start_setup / ns_per_clk;
307 writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP);
308
309 /* Start hold time */
310 val = t->start_hold / ns_per_clk;
311 writel_relaxed(val, i2c_dev->base + SSC_START_HOLD);
312
313 /* Data set up time */
314 val = t->data_setup_time / ns_per_clk;
315 writel_relaxed(val, i2c_dev->base + SSC_DATA_SETUP);
316
317 /* Stop set up time */
318 val = t->stop_setup_time / ns_per_clk;
319 writel_relaxed(val, i2c_dev->base + SSC_STOP_SETUP);
320
321 /* Bus free time */
322 val = t->bus_free_time / ns_per_clk;
323 writel_relaxed(val, i2c_dev->base + SSC_BUS_FREE);
324
325 /* Prescalers set up */
326 val = rate / 10000000;
327 writel_relaxed(val, i2c_dev->base + SSC_PRSCALER);
328 writel_relaxed(val, i2c_dev->base + SSC_PRSCALER_DATAOUT);
329
330 /* Noise suppression witdh */
331 val = i2c_dev->scl_min_width_us * rate / 100000000;
332 writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH);
333
334 /* Noise suppression max output data delay width */
335 val = i2c_dev->sda_min_width_us * rate / 100000000;
336 writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH_DATAOUT);
337 }
338
st_i2c_recover_bus(struct i2c_adapter * i2c_adap)339 static int st_i2c_recover_bus(struct i2c_adapter *i2c_adap)
340 {
341 struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
342 u32 ctl;
343
344 dev_dbg(i2c_dev->dev, "Trying to recover bus\n");
345
346 /*
347 * SSP IP is dual role SPI/I2C to generate 9 clock pulses
348 * we switch to SPI node, 9 bit words and write a 0. This
349 * has been validate with a oscilloscope and is easier
350 * than switching to GPIO mode.
351 */
352
353 /* Disable interrupts */
354 writel_relaxed(0, i2c_dev->base + SSC_IEN);
355
356 st_i2c_hw_config(i2c_dev);
357
358 ctl = SSC_CTL_EN | SSC_CTL_MS | SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO;
359 st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl);
360
361 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_I2CM);
362 usleep_range(8000, 10000);
363
364 writel_relaxed(0, i2c_dev->base + SSC_TBUF);
365 usleep_range(2000, 4000);
366 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_I2CM);
367
368 return 0;
369 }
370
st_i2c_wait_free_bus(struct st_i2c_dev * i2c_dev)371 static int st_i2c_wait_free_bus(struct st_i2c_dev *i2c_dev)
372 {
373 u32 sta;
374 int i, ret;
375
376 for (i = 0; i < 10; i++) {
377 sta = readl_relaxed(i2c_dev->base + SSC_STA);
378 if (!(sta & SSC_STA_BUSY))
379 return 0;
380
381 usleep_range(2000, 4000);
382 }
383
384 dev_err(i2c_dev->dev, "bus not free (status = 0x%08x)\n", sta);
385
386 ret = i2c_recover_bus(&i2c_dev->adap);
387 if (ret) {
388 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
389 return ret;
390 }
391
392 return -EBUSY;
393 }
394
395 /**
396 * st_i2c_write_tx_fifo() - Write a byte in the Tx FIFO
397 * @i2c_dev: Controller's private data
398 * @byte: Data to write in the Tx FIFO
399 */
st_i2c_write_tx_fifo(struct st_i2c_dev * i2c_dev,u8 byte)400 static inline void st_i2c_write_tx_fifo(struct st_i2c_dev *i2c_dev, u8 byte)
401 {
402 u16 tbuf = byte << 1;
403
404 writel_relaxed(tbuf | 1, i2c_dev->base + SSC_TBUF);
405 }
406
407 /**
408 * st_i2c_wr_fill_tx_fifo() - Fill the Tx FIFO in write mode
409 * @i2c_dev: Controller's private data
410 *
411 * This functions fills the Tx FIFO with I2C transfert buffer when
412 * in write mode.
413 */
st_i2c_wr_fill_tx_fifo(struct st_i2c_dev * i2c_dev)414 static void st_i2c_wr_fill_tx_fifo(struct st_i2c_dev *i2c_dev)
415 {
416 struct st_i2c_client *c = &i2c_dev->client;
417 u32 tx_fstat, sta;
418 int i;
419
420 sta = readl_relaxed(i2c_dev->base + SSC_STA);
421 if (sta & SSC_STA_TX_FIFO_FULL)
422 return;
423
424 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT);
425 tx_fstat &= SSC_TX_FSTAT_STATUS;
426
427 for (i = min(c->count, SSC_TXFIFO_SIZE - tx_fstat);
428 i > 0; i--, c->count--, c->buf++)
429 st_i2c_write_tx_fifo(i2c_dev, *c->buf);
430 }
431
432 /**
433 * st_i2c_rd_fill_tx_fifo() - Fill the Tx FIFO in read mode
434 * @i2c_dev: Controller's private data
435 * @max: Maximum amount of data to fill into the Tx FIFO
436 *
437 * This functions fills the Tx FIFO with fixed pattern when
438 * in read mode to trigger clock.
439 */
st_i2c_rd_fill_tx_fifo(struct st_i2c_dev * i2c_dev,u32 max)440 static void st_i2c_rd_fill_tx_fifo(struct st_i2c_dev *i2c_dev, u32 max)
441 {
442 struct st_i2c_client *c = &i2c_dev->client;
443 u32 tx_fstat, sta;
444 int i;
445
446 sta = readl_relaxed(i2c_dev->base + SSC_STA);
447 if (sta & SSC_STA_TX_FIFO_FULL)
448 return;
449
450 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT);
451 tx_fstat &= SSC_TX_FSTAT_STATUS;
452
453 for (i = min(max, SSC_TXFIFO_SIZE - tx_fstat);
454 i > 0; i--, c->xfered++)
455 st_i2c_write_tx_fifo(i2c_dev, 0xff);
456 }
457
st_i2c_read_rx_fifo(struct st_i2c_dev * i2c_dev)458 static void st_i2c_read_rx_fifo(struct st_i2c_dev *i2c_dev)
459 {
460 struct st_i2c_client *c = &i2c_dev->client;
461 u32 i, sta;
462 u16 rbuf;
463
464 sta = readl_relaxed(i2c_dev->base + SSC_STA);
465 if (sta & SSC_STA_RIR) {
466 i = SSC_RXFIFO_SIZE;
467 } else {
468 i = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT);
469 i &= SSC_RX_FSTAT_STATUS;
470 }
471
472 for (; (i > 0) && (c->count > 0); i--, c->count--) {
473 rbuf = readl_relaxed(i2c_dev->base + SSC_RBUF) >> 1;
474 *c->buf++ = (u8)rbuf & 0xff;
475 }
476
477 if (i) {
478 dev_err(i2c_dev->dev, "Unexpected %d bytes in rx fifo\n", i);
479 st_i2c_flush_rx_fifo(i2c_dev);
480 }
481 }
482
483 /**
484 * st_i2c_terminate_xfer() - Send either STOP or REPSTART condition
485 * @i2c_dev: Controller's private data
486 */
st_i2c_terminate_xfer(struct st_i2c_dev * i2c_dev)487 static void st_i2c_terminate_xfer(struct st_i2c_dev *i2c_dev)
488 {
489 struct st_i2c_client *c = &i2c_dev->client;
490
491 st_i2c_clr_bits(i2c_dev->base + SSC_IEN, SSC_IEN_TEEN);
492 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG);
493
494 if (c->stop) {
495 st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_STOPEN);
496 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
497 } else {
498 st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_REPSTRTEN);
499 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_REPSTRTG);
500 }
501 }
502
503 /**
504 * st_i2c_handle_write() - Handle FIFO empty interrupt in case of write
505 * @i2c_dev: Controller's private data
506 */
st_i2c_handle_write(struct st_i2c_dev * i2c_dev)507 static void st_i2c_handle_write(struct st_i2c_dev *i2c_dev)
508 {
509 struct st_i2c_client *c = &i2c_dev->client;
510
511 st_i2c_flush_rx_fifo(i2c_dev);
512
513 if (!c->count)
514 /* End of xfer, send stop or repstart */
515 st_i2c_terminate_xfer(i2c_dev);
516 else
517 st_i2c_wr_fill_tx_fifo(i2c_dev);
518 }
519
520 /**
521 * st_i2c_handle_read() - Handle FIFO empty interrupt in case of read
522 * @i2c_dev: Controller's private data
523 */
st_i2c_handle_read(struct st_i2c_dev * i2c_dev)524 static void st_i2c_handle_read(struct st_i2c_dev *i2c_dev)
525 {
526 struct st_i2c_client *c = &i2c_dev->client;
527 u32 ien;
528
529 /* Trash the address read back */
530 if (!c->xfered) {
531 readl_relaxed(i2c_dev->base + SSC_RBUF);
532 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_TXENB);
533 } else {
534 st_i2c_read_rx_fifo(i2c_dev);
535 }
536
537 if (!c->count) {
538 /* End of xfer, send stop or repstart */
539 st_i2c_terminate_xfer(i2c_dev);
540 } else if (c->count == 1) {
541 /* Penultimate byte to xfer, disable ACK gen. */
542 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_ACKG);
543
544 /* Last received byte is to be handled by NACK interrupt */
545 ien = SSC_IEN_NACKEN | SSC_IEN_ARBLEN;
546 writel_relaxed(ien, i2c_dev->base + SSC_IEN);
547
548 st_i2c_rd_fill_tx_fifo(i2c_dev, c->count);
549 } else {
550 st_i2c_rd_fill_tx_fifo(i2c_dev, c->count - 1);
551 }
552 }
553
554 /**
555 * st_i2c_isr_thread() - Interrupt routine
556 * @irq: interrupt number
557 * @data: Controller's private data
558 */
st_i2c_isr_thread(int irq,void * data)559 static irqreturn_t st_i2c_isr_thread(int irq, void *data)
560 {
561 struct st_i2c_dev *i2c_dev = data;
562 struct st_i2c_client *c = &i2c_dev->client;
563 u32 sta, ien;
564 int it;
565
566 ien = readl_relaxed(i2c_dev->base + SSC_IEN);
567 sta = readl_relaxed(i2c_dev->base + SSC_STA);
568
569 /* Use __fls() to check error bits first */
570 it = __fls(sta & ien);
571 if (it < 0) {
572 dev_dbg(i2c_dev->dev, "spurious it (sta=0x%04x, ien=0x%04x)\n",
573 sta, ien);
574 return IRQ_NONE;
575 }
576
577 switch (1 << it) {
578 case SSC_STA_TE:
579 if (c->addr & I2C_M_RD)
580 st_i2c_handle_read(i2c_dev);
581 else
582 st_i2c_handle_write(i2c_dev);
583 break;
584
585 case SSC_STA_STOP:
586 case SSC_STA_REPSTRT:
587 writel_relaxed(0, i2c_dev->base + SSC_IEN);
588 complete(&i2c_dev->complete);
589 break;
590
591 case SSC_STA_NACK:
592 writel_relaxed(SSC_CLR_NACK, i2c_dev->base + SSC_CLR);
593
594 /* Last received byte handled by NACK interrupt */
595 if ((c->addr & I2C_M_RD) && (c->count == 1) && (c->xfered)) {
596 st_i2c_handle_read(i2c_dev);
597 break;
598 }
599
600 it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN;
601 writel_relaxed(it, i2c_dev->base + SSC_IEN);
602
603 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
604 c->result = -EIO;
605 break;
606
607 case SSC_STA_ARBL:
608 writel_relaxed(SSC_CLR_SSCARBL, i2c_dev->base + SSC_CLR);
609
610 it = SSC_IEN_STOPEN | SSC_IEN_ARBLEN;
611 writel_relaxed(it, i2c_dev->base + SSC_IEN);
612
613 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG);
614 c->result = -EAGAIN;
615 break;
616
617 default:
618 dev_err(i2c_dev->dev,
619 "it %d unhandled (sta=0x%04x)\n", it, sta);
620 }
621
622 /*
623 * Read IEN register to ensure interrupt mask write is effective
624 * before re-enabling interrupt at GIC level, and thus avoid spurious
625 * interrupts.
626 */
627 readl(i2c_dev->base + SSC_IEN);
628
629 return IRQ_HANDLED;
630 }
631
632 /**
633 * st_i2c_xfer_msg() - Transfer a single I2C message
634 * @i2c_dev: Controller's private data
635 * @msg: I2C message to transfer
636 * @is_first: first message of the sequence
637 * @is_last: last message of the sequence
638 */
st_i2c_xfer_msg(struct st_i2c_dev * i2c_dev,struct i2c_msg * msg,bool is_first,bool is_last)639 static int st_i2c_xfer_msg(struct st_i2c_dev *i2c_dev, struct i2c_msg *msg,
640 bool is_first, bool is_last)
641 {
642 struct st_i2c_client *c = &i2c_dev->client;
643 u32 ctl, i2c, it;
644 unsigned long time_left;
645 int ret;
646
647 c->addr = i2c_8bit_addr_from_msg(msg);
648 c->buf = msg->buf;
649 c->count = msg->len;
650 c->xfered = 0;
651 c->result = 0;
652 c->stop = is_last;
653
654 reinit_completion(&i2c_dev->complete);
655
656 ctl = SSC_CTL_EN | SSC_CTL_MS | SSC_CTL_EN_RX_FIFO | SSC_CTL_EN_TX_FIFO;
657 st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl);
658
659 i2c = SSC_I2C_TXENB;
660 if (c->addr & I2C_M_RD)
661 i2c |= SSC_I2C_ACKG;
662 st_i2c_set_bits(i2c_dev->base + SSC_I2C, i2c);
663
664 /* Write target address */
665 st_i2c_write_tx_fifo(i2c_dev, c->addr);
666
667 /* Pre-fill Tx fifo with data in case of write */
668 if (!(c->addr & I2C_M_RD))
669 st_i2c_wr_fill_tx_fifo(i2c_dev);
670
671 it = SSC_IEN_NACKEN | SSC_IEN_TEEN | SSC_IEN_ARBLEN;
672 writel_relaxed(it, i2c_dev->base + SSC_IEN);
673
674 if (is_first) {
675 ret = st_i2c_wait_free_bus(i2c_dev);
676 if (ret)
677 return ret;
678
679 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG);
680 }
681
682 time_left = wait_for_completion_timeout(&i2c_dev->complete,
683 i2c_dev->adap.timeout);
684 ret = c->result;
685
686 if (!time_left)
687 ret = -ETIMEDOUT;
688
689 i2c = SSC_I2C_STOPG | SSC_I2C_REPSTRTG;
690 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, i2c);
691
692 writel_relaxed(SSC_CLR_SSCSTOP | SSC_CLR_REPSTRT,
693 i2c_dev->base + SSC_CLR);
694
695 return ret;
696 }
697
698 /**
699 * st_i2c_xfer() - Transfer a single I2C message
700 * @i2c_adap: Adapter pointer to the controller
701 * @msgs: Pointer to data to be written.
702 * @num: Number of messages to be executed
703 */
st_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg msgs[],int num)704 static int st_i2c_xfer(struct i2c_adapter *i2c_adap,
705 struct i2c_msg msgs[], int num)
706 {
707 struct st_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
708 int ret, i;
709
710 i2c_dev->busy = true;
711
712 ret = clk_prepare_enable(i2c_dev->clk);
713 if (ret) {
714 dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n");
715 return ret;
716 }
717
718 pinctrl_pm_select_default_state(i2c_dev->dev);
719
720 st_i2c_hw_config(i2c_dev);
721
722 for (i = 0; (i < num) && !ret; i++)
723 ret = st_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, i == num - 1);
724
725 pinctrl_pm_select_idle_state(i2c_dev->dev);
726
727 clk_disable_unprepare(i2c_dev->clk);
728
729 i2c_dev->busy = false;
730
731 return (ret < 0) ? ret : i;
732 }
733
st_i2c_suspend(struct device * dev)734 static int st_i2c_suspend(struct device *dev)
735 {
736 struct st_i2c_dev *i2c_dev = dev_get_drvdata(dev);
737
738 if (i2c_dev->busy)
739 return -EBUSY;
740
741 pinctrl_pm_select_sleep_state(dev);
742
743 return 0;
744 }
745
st_i2c_resume(struct device * dev)746 static int st_i2c_resume(struct device *dev)
747 {
748 pinctrl_pm_select_default_state(dev);
749 /* Go in idle state if available */
750 pinctrl_pm_select_idle_state(dev);
751
752 return 0;
753 }
754
755 static DEFINE_SIMPLE_DEV_PM_OPS(st_i2c_pm, st_i2c_suspend, st_i2c_resume);
756
st_i2c_func(struct i2c_adapter * adap)757 static u32 st_i2c_func(struct i2c_adapter *adap)
758 {
759 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
760 }
761
762 static const struct i2c_algorithm st_i2c_algo = {
763 .xfer = st_i2c_xfer,
764 .functionality = st_i2c_func,
765 };
766
767 static struct i2c_bus_recovery_info st_i2c_recovery_info = {
768 .recover_bus = st_i2c_recover_bus,
769 };
770
st_i2c_of_get_deglitch(struct device_node * np,struct st_i2c_dev * i2c_dev)771 static int st_i2c_of_get_deglitch(struct device_node *np,
772 struct st_i2c_dev *i2c_dev)
773 {
774 int ret;
775
776 ret = of_property_read_u32(np, "st,i2c-min-scl-pulse-width-us",
777 &i2c_dev->scl_min_width_us);
778 if ((ret == -ENODATA) || (ret == -EOVERFLOW)) {
779 dev_err(i2c_dev->dev, "st,i2c-min-scl-pulse-width-us invalid\n");
780 return ret;
781 }
782
783 ret = of_property_read_u32(np, "st,i2c-min-sda-pulse-width-us",
784 &i2c_dev->sda_min_width_us);
785 if ((ret == -ENODATA) || (ret == -EOVERFLOW)) {
786 dev_err(i2c_dev->dev, "st,i2c-min-sda-pulse-width-us invalid\n");
787 return ret;
788 }
789
790 return 0;
791 }
792
st_i2c_probe(struct platform_device * pdev)793 static int st_i2c_probe(struct platform_device *pdev)
794 {
795 struct device_node *np = pdev->dev.of_node;
796 struct st_i2c_dev *i2c_dev;
797 struct resource *res;
798 u32 clk_rate;
799 struct i2c_adapter *adap;
800 int ret;
801
802 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
803 if (!i2c_dev)
804 return -ENOMEM;
805
806 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
807 if (IS_ERR(i2c_dev->base))
808 return PTR_ERR(i2c_dev->base);
809
810 i2c_dev->irq = irq_of_parse_and_map(np, 0);
811 if (!i2c_dev->irq) {
812 dev_err(&pdev->dev, "IRQ missing or invalid\n");
813 return -EINVAL;
814 }
815
816 i2c_dev->clk = of_clk_get_by_name(np, "ssc");
817 if (IS_ERR(i2c_dev->clk)) {
818 dev_err(&pdev->dev, "Unable to request clock\n");
819 return PTR_ERR(i2c_dev->clk);
820 }
821
822 i2c_dev->mode = I2C_MODE_STANDARD;
823 ret = of_property_read_u32(np, "clock-frequency", &clk_rate);
824 if (!ret && (clk_rate == I2C_MAX_FAST_MODE_FREQ))
825 i2c_dev->mode = I2C_MODE_FAST;
826
827 i2c_dev->dev = &pdev->dev;
828
829 ret = devm_request_threaded_irq(&pdev->dev, i2c_dev->irq,
830 NULL, st_i2c_isr_thread,
831 IRQF_ONESHOT, pdev->name, i2c_dev);
832 if (ret) {
833 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
834 return ret;
835 }
836
837 pinctrl_pm_select_default_state(i2c_dev->dev);
838 /* In case idle state available, select it */
839 pinctrl_pm_select_idle_state(i2c_dev->dev);
840
841 ret = st_i2c_of_get_deglitch(np, i2c_dev);
842 if (ret)
843 return ret;
844
845 adap = &i2c_dev->adap;
846 i2c_set_adapdata(adap, i2c_dev);
847 snprintf(adap->name, sizeof(adap->name), "ST I2C(%pa)", &res->start);
848 adap->owner = THIS_MODULE;
849 adap->timeout = 2 * HZ;
850 adap->retries = 0;
851 adap->algo = &st_i2c_algo;
852 adap->bus_recovery_info = &st_i2c_recovery_info;
853 adap->dev.parent = &pdev->dev;
854 adap->dev.of_node = pdev->dev.of_node;
855
856 init_completion(&i2c_dev->complete);
857
858 ret = i2c_add_adapter(adap);
859 if (ret)
860 return ret;
861
862 platform_set_drvdata(pdev, i2c_dev);
863
864 dev_info(i2c_dev->dev, "%s initialized\n", adap->name);
865
866 return 0;
867 }
868
st_i2c_remove(struct platform_device * pdev)869 static void st_i2c_remove(struct platform_device *pdev)
870 {
871 struct st_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
872
873 i2c_del_adapter(&i2c_dev->adap);
874 }
875
876 static const struct of_device_id st_i2c_match[] = {
877 { .compatible = "st,comms-ssc-i2c", },
878 { .compatible = "st,comms-ssc4-i2c", },
879 {},
880 };
881 MODULE_DEVICE_TABLE(of, st_i2c_match);
882
883 static struct platform_driver st_i2c_driver = {
884 .driver = {
885 .name = "st-i2c",
886 .of_match_table = st_i2c_match,
887 .pm = pm_sleep_ptr(&st_i2c_pm),
888 },
889 .probe = st_i2c_probe,
890 .remove = st_i2c_remove,
891 };
892
893 module_platform_driver(st_i2c_driver);
894
895 MODULE_AUTHOR("Maxime Coquelin <maxime.coquelin@st.com>");
896 MODULE_DESCRIPTION("STMicroelectronics I2C driver");
897 MODULE_LICENSE("GPL v2");
898