1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
6 *
7 * This code was implemented by Mocean Laboratories AB when porting linux
8 * to the automotive development board Russellville. The copyright holder
9 * as seen in the header is Intel corporation.
10 * Mocean Laboratories forked off the GNU/Linux platform work into a
11 * separate company called Pelagicore AB, which committed the code to the
12 * kernel.
13 */
14
15 /* Supports:
16 * Xilinx IIC
17 */
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
23 #include <linux/platform_device.h>
24 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
26 #include <linux/completion.h>
27 #include <linux/platform_data/i2c-xiic.h>
28 #include <linux/io.h>
29 #include <linux/slab.h>
30 #include <linux/clk.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/iopoll.h>
33 #include <linux/spinlock.h>
34
35 #define DRIVER_NAME "xiic-i2c"
36 #define DYNAMIC_MODE_READ_BROKEN_BIT BIT(0)
37 #define SMBUS_BLOCK_READ_MIN_LEN 3
38
39 enum xilinx_i2c_state {
40 STATE_DONE,
41 STATE_ERROR,
42 STATE_START
43 };
44
45 enum xiic_endian {
46 LITTLE,
47 BIG
48 };
49
50 enum i2c_scl_freq {
51 REG_VALUES_100KHZ = 0,
52 REG_VALUES_400KHZ = 1,
53 REG_VALUES_1MHZ = 2
54 };
55
56 /**
57 * struct xiic_i2c - Internal representation of the XIIC I2C bus
58 * @dev: Pointer to device structure
59 * @base: Memory base of the HW registers
60 * @completion: Completion for callers
61 * @adap: Kernel adapter representation
62 * @tx_msg: Messages from above to be sent
63 * @lock: Mutual exclusion
64 * @tx_pos: Current pos in TX message
65 * @nmsgs: Number of messages in tx_msg
66 * @rx_msg: Current RX message
67 * @rx_pos: Position within current RX message
68 * @endianness: big/little-endian byte order
69 * @clk: Pointer to AXI4-lite input clock
70 * @state: See STATE_
71 * @singlemaster: Indicates bus is single master
72 * @dynamic: Mode of controller
73 * @prev_msg_tx: Previous message is Tx
74 * @quirks: To hold platform specific bug info
75 * @smbus_block_read: Flag to handle block read
76 * @input_clk: Input clock to I2C controller
77 * @i2c_clk: I2C SCL frequency
78 * @atomic: Mode of transfer
79 * @atomic_lock: Lock for atomic transfer mode
80 * @atomic_xfer_state: See STATE_
81 */
82 struct xiic_i2c {
83 struct device *dev;
84 void __iomem *base;
85 struct completion completion;
86 struct i2c_adapter adap;
87 struct i2c_msg *tx_msg;
88 struct mutex lock;
89 unsigned int tx_pos;
90 unsigned int nmsgs;
91 struct i2c_msg *rx_msg;
92 int rx_pos;
93 enum xiic_endian endianness;
94 struct clk *clk;
95 enum xilinx_i2c_state state;
96 bool singlemaster;
97 bool dynamic;
98 bool prev_msg_tx;
99 u32 quirks;
100 bool smbus_block_read;
101 unsigned long input_clk;
102 unsigned int i2c_clk;
103 bool atomic;
104 spinlock_t atomic_lock; /* Lock for atomic transfer mode */
105 enum xilinx_i2c_state atomic_xfer_state;
106 };
107
108 struct xiic_version_data {
109 u32 quirks;
110 };
111
112 /**
113 * struct timing_regs - AXI I2C timing registers that depend on I2C spec
114 * @tsusta: setup time for a repeated START condition
115 * @tsusto: setup time for a STOP condition
116 * @thdsta: hold time for a repeated START condition
117 * @tsudat: setup time for data
118 * @tbuf: bus free time between STOP and START
119 */
120 struct timing_regs {
121 unsigned int tsusta;
122 unsigned int tsusto;
123 unsigned int thdsta;
124 unsigned int tsudat;
125 unsigned int tbuf;
126 };
127
128 /* Reg values in ns derived from I2C spec and AXI I2C PG for different frequencies */
129 static const struct timing_regs timing_reg_values[] = {
130 { 5700, 5000, 4300, 550, 5000 }, /* Reg values for 100KHz */
131 { 900, 900, 900, 400, 1600 }, /* Reg values for 400KHz */
132 { 380, 380, 380, 170, 620 }, /* Reg values for 1MHz */
133 };
134
135 #define XIIC_MSB_OFFSET 0
136 #define XIIC_REG_OFFSET (0x100 + XIIC_MSB_OFFSET)
137
138 /*
139 * Register offsets in bytes from RegisterBase. Three is added to the
140 * base offset to access LSB (IBM style) of the word
141 */
142 #define XIIC_CR_REG_OFFSET (0x00 + XIIC_REG_OFFSET) /* Control Register */
143 #define XIIC_SR_REG_OFFSET (0x04 + XIIC_REG_OFFSET) /* Status Register */
144 #define XIIC_DTR_REG_OFFSET (0x08 + XIIC_REG_OFFSET) /* Data Tx Register */
145 #define XIIC_DRR_REG_OFFSET (0x0C + XIIC_REG_OFFSET) /* Data Rx Register */
146 #define XIIC_ADR_REG_OFFSET (0x10 + XIIC_REG_OFFSET) /* Address Register */
147 #define XIIC_TFO_REG_OFFSET (0x14 + XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
148 #define XIIC_RFO_REG_OFFSET (0x18 + XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
149 #define XIIC_TBA_REG_OFFSET (0x1C + XIIC_REG_OFFSET) /* 10 Bit Address reg */
150 #define XIIC_RFD_REG_OFFSET (0x20 + XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
151 #define XIIC_GPO_REG_OFFSET (0x24 + XIIC_REG_OFFSET) /* Output Register */
152
153 /*
154 * Timing register offsets from RegisterBase. These are used only for
155 * setting i2c clock frequency for the line.
156 */
157 #define XIIC_TSUSTA_REG_OFFSET (0x28 + XIIC_REG_OFFSET) /* TSUSTA Register */
158 #define XIIC_TSUSTO_REG_OFFSET (0x2C + XIIC_REG_OFFSET) /* TSUSTO Register */
159 #define XIIC_THDSTA_REG_OFFSET (0x30 + XIIC_REG_OFFSET) /* THDSTA Register */
160 #define XIIC_TSUDAT_REG_OFFSET (0x34 + XIIC_REG_OFFSET) /* TSUDAT Register */
161 #define XIIC_TBUF_REG_OFFSET (0x38 + XIIC_REG_OFFSET) /* TBUF Register */
162 #define XIIC_THIGH_REG_OFFSET (0x3C + XIIC_REG_OFFSET) /* THIGH Register */
163 #define XIIC_TLOW_REG_OFFSET (0x40 + XIIC_REG_OFFSET) /* TLOW Register */
164 #define XIIC_THDDAT_REG_OFFSET (0x44 + XIIC_REG_OFFSET) /* THDDAT Register */
165
166 /* Control Register masks */
167 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
168 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
169 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
170 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
171 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
172 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
173 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
174
175 /* Status Register masks */
176 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
177 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
178 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
179 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
180 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
181 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
182 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
183 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
184
185 /* Interrupt Status Register masks Interrupt occurs when... */
186 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
187 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
188 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
189 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
190 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
191 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
192 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
193 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
194
195 /* The following constants specify the depth of the FIFOs */
196 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
197 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
198
199 /* The following constants specify groups of interrupts that are typically
200 * enabled or disables at the same time
201 */
202 #define XIIC_TX_INTERRUPTS \
203 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
204
205 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
206
207 /*
208 * Tx Fifo upper bit masks.
209 */
210 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
211 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
212
213 /* Dynamic mode constants */
214 #define MAX_READ_LENGTH_DYNAMIC 255 /* Max length for dynamic read */
215
216 /*
217 * The following constants define the register offsets for the Interrupt
218 * registers. There are some holes in the memory map for reserved addresses
219 * to allow other registers to be added and still match the memory map of the
220 * interrupt controller registers
221 */
222 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
223 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
224 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
225 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
226
227 #define XIIC_RESET_MASK 0xAUL
228
229 #define XIIC_PM_TIMEOUT 1000 /* ms */
230 /* timeout waiting for the controller to respond */
231 #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000))
232 /* timeout waiting for the controller finish transfers */
233 #define XIIC_XFER_TIMEOUT (msecs_to_jiffies(10000))
234 /* timeout waiting for the controller finish transfers in micro seconds */
235 #define XIIC_XFER_TIMEOUT_US 10000000
236
237 /*
238 * The following constant is used for the device global interrupt enable
239 * register, to enable all interrupts for the device, this is the only bit
240 * in the register
241 */
242 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL
243
244 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
245 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
246
247 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num);
248 static void __xiic_start_xfer(struct xiic_i2c *i2c);
249
xiic_i2c_runtime_suspend(struct device * dev)250 static int xiic_i2c_runtime_suspend(struct device *dev)
251 {
252 struct xiic_i2c *i2c = dev_get_drvdata(dev);
253
254 clk_disable(i2c->clk);
255
256 return 0;
257 }
258
xiic_i2c_runtime_resume(struct device * dev)259 static int xiic_i2c_runtime_resume(struct device *dev)
260 {
261 struct xiic_i2c *i2c = dev_get_drvdata(dev);
262 int ret;
263
264 ret = clk_enable(i2c->clk);
265 if (ret) {
266 dev_err(dev, "Cannot enable clock.\n");
267 return ret;
268 }
269
270 return 0;
271 }
272
273 /*
274 * For the register read and write functions, a little-endian and big-endian
275 * version are necessary. Endianness is detected during the probe function.
276 * Only the least significant byte [doublet] of the register are ever
277 * accessed. This requires an offset of 3 [2] from the base address for
278 * big-endian systems.
279 */
280
xiic_setreg8(struct xiic_i2c * i2c,int reg,u8 value)281 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
282 {
283 if (i2c->endianness == LITTLE)
284 iowrite8(value, i2c->base + reg);
285 else
286 iowrite8(value, i2c->base + reg + 3);
287 }
288
xiic_getreg8(struct xiic_i2c * i2c,int reg)289 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
290 {
291 u8 ret;
292
293 if (i2c->endianness == LITTLE)
294 ret = ioread8(i2c->base + reg);
295 else
296 ret = ioread8(i2c->base + reg + 3);
297 return ret;
298 }
299
xiic_setreg16(struct xiic_i2c * i2c,int reg,u16 value)300 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
301 {
302 if (i2c->endianness == LITTLE)
303 iowrite16(value, i2c->base + reg);
304 else
305 iowrite16be(value, i2c->base + reg + 2);
306 }
307
xiic_setreg32(struct xiic_i2c * i2c,int reg,int value)308 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
309 {
310 if (i2c->endianness == LITTLE)
311 iowrite32(value, i2c->base + reg);
312 else
313 iowrite32be(value, i2c->base + reg);
314 }
315
xiic_getreg32(struct xiic_i2c * i2c,int reg)316 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
317 {
318 u32 ret;
319
320 if (i2c->endianness == LITTLE)
321 ret = ioread32(i2c->base + reg);
322 else
323 ret = ioread32be(i2c->base + reg);
324 return ret;
325 }
326
xiic_irq_dis(struct xiic_i2c * i2c,u32 mask)327 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
328 {
329 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
330
331 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
332 }
333
xiic_irq_en(struct xiic_i2c * i2c,u32 mask)334 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
335 {
336 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
337
338 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
339 }
340
xiic_irq_clr(struct xiic_i2c * i2c,u32 mask)341 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
342 {
343 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
344
345 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
346 }
347
xiic_irq_clr_en(struct xiic_i2c * i2c,u32 mask)348 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
349 {
350 xiic_irq_clr(i2c, mask);
351 xiic_irq_en(i2c, mask);
352 }
353
xiic_clear_rx_fifo(struct xiic_i2c * i2c)354 static int xiic_clear_rx_fifo(struct xiic_i2c *i2c)
355 {
356 u8 sr;
357 unsigned long timeout;
358
359 timeout = jiffies + XIIC_I2C_TIMEOUT;
360 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
361 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
362 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) {
363 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
364 if (time_after(jiffies, timeout)) {
365 dev_err(i2c->dev, "Failed to clear rx fifo\n");
366 return -ETIMEDOUT;
367 }
368 }
369
370 return 0;
371 }
372
xiic_wait_tx_empty(struct xiic_i2c * i2c)373 static int xiic_wait_tx_empty(struct xiic_i2c *i2c)
374 {
375 u8 isr;
376 unsigned long timeout;
377
378 timeout = jiffies + XIIC_I2C_TIMEOUT;
379 for (isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
380 !(isr & XIIC_INTR_TX_EMPTY_MASK);
381 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET)) {
382 if (time_after(jiffies, timeout)) {
383 dev_err(i2c->dev, "Timeout waiting at Tx empty\n");
384 return -ETIMEDOUT;
385 }
386 }
387
388 return 0;
389 }
390
391 /**
392 * xiic_setclk - Sets the configured clock rate
393 * @i2c: Pointer to the xiic device structure
394 *
395 * The timing register values are calculated according to the input clock
396 * frequency and configured scl frequency. For details, please refer the
397 * AXI I2C PG and NXP I2C Spec.
398 * Supported frequencies are 100KHz, 400KHz and 1MHz.
399 *
400 * Return: 0 on success (Supported frequency selected or not configurable in SW)
401 * -EINVAL on failure (scl frequency not supported or THIGH is 0)
402 */
xiic_setclk(struct xiic_i2c * i2c)403 static int xiic_setclk(struct xiic_i2c *i2c)
404 {
405 unsigned int clk_in_mhz;
406 unsigned int index = 0;
407 u32 reg_val;
408
409 if (!i2c->atomic)
410 dev_dbg(i2c->adap.dev.parent,
411 "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n",
412 __func__, i2c->input_clk, i2c->i2c_clk);
413
414 /* If not specified in DT, do not configure in SW. Rely only on Vivado design */
415 if (!i2c->i2c_clk || !i2c->input_clk)
416 return 0;
417
418 clk_in_mhz = DIV_ROUND_UP(i2c->input_clk, 1000000);
419
420 switch (i2c->i2c_clk) {
421 case I2C_MAX_FAST_MODE_PLUS_FREQ:
422 index = REG_VALUES_1MHZ;
423 break;
424 case I2C_MAX_FAST_MODE_FREQ:
425 index = REG_VALUES_400KHZ;
426 break;
427 case I2C_MAX_STANDARD_MODE_FREQ:
428 index = REG_VALUES_100KHZ;
429 break;
430 default:
431 dev_warn(i2c->adap.dev.parent, "Unsupported scl frequency\n");
432 return -EINVAL;
433 }
434
435 /*
436 * Value to be stored in a register is the number of clock cycles required
437 * for the time duration. So the time is divided by the input clock time
438 * period to get the number of clock cycles required. Refer Xilinx AXI I2C
439 * PG document and I2C specification for further details.
440 */
441
442 /* THIGH - Depends on SCL clock frequency(i2c_clk) as below */
443 reg_val = (DIV_ROUND_UP(i2c->input_clk, 2 * i2c->i2c_clk)) - 7;
444 if (reg_val == 0)
445 return -EINVAL;
446
447 xiic_setreg32(i2c, XIIC_THIGH_REG_OFFSET, reg_val - 1);
448
449 /* TLOW - Value same as THIGH */
450 xiic_setreg32(i2c, XIIC_TLOW_REG_OFFSET, reg_val - 1);
451
452 /* TSUSTA */
453 reg_val = (timing_reg_values[index].tsusta * clk_in_mhz) / 1000;
454 xiic_setreg32(i2c, XIIC_TSUSTA_REG_OFFSET, reg_val - 1);
455
456 /* TSUSTO */
457 reg_val = (timing_reg_values[index].tsusto * clk_in_mhz) / 1000;
458 xiic_setreg32(i2c, XIIC_TSUSTO_REG_OFFSET, reg_val - 1);
459
460 /* THDSTA */
461 reg_val = (timing_reg_values[index].thdsta * clk_in_mhz) / 1000;
462 xiic_setreg32(i2c, XIIC_THDSTA_REG_OFFSET, reg_val - 1);
463
464 /* TSUDAT */
465 reg_val = (timing_reg_values[index].tsudat * clk_in_mhz) / 1000;
466 xiic_setreg32(i2c, XIIC_TSUDAT_REG_OFFSET, reg_val - 1);
467
468 /* TBUF */
469 reg_val = (timing_reg_values[index].tbuf * clk_in_mhz) / 1000;
470 xiic_setreg32(i2c, XIIC_TBUF_REG_OFFSET, reg_val - 1);
471
472 /* THDDAT */
473 xiic_setreg32(i2c, XIIC_THDDAT_REG_OFFSET, 1);
474
475 return 0;
476 }
477
xiic_reinit(struct xiic_i2c * i2c)478 static int xiic_reinit(struct xiic_i2c *i2c)
479 {
480 int ret;
481
482 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
483
484 ret = xiic_setclk(i2c);
485 if (ret)
486 return ret;
487
488 /* Set receive Fifo depth to maximum (zero based). */
489 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
490
491 /* Reset Tx Fifo. */
492 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
493
494 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
495 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
496
497 /* make sure RX fifo is empty */
498 ret = xiic_clear_rx_fifo(i2c);
499 if (ret)
500 return ret;
501
502 /* Enable interrupts */
503 if (!i2c->atomic)
504 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
505
506 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
507
508 return 0;
509 }
510
xiic_deinit(struct xiic_i2c * i2c)511 static void xiic_deinit(struct xiic_i2c *i2c)
512 {
513 u8 cr;
514
515 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
516
517 /* Disable IIC Device. */
518 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
519 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
520 }
521
xiic_smbus_block_read_setup(struct xiic_i2c * i2c)522 static void xiic_smbus_block_read_setup(struct xiic_i2c *i2c)
523 {
524 u8 rxmsg_len, rfd_set = 0;
525
526 /*
527 * Clear the I2C_M_RECV_LEN flag to avoid setting
528 * message length again
529 */
530 i2c->rx_msg->flags &= ~I2C_M_RECV_LEN;
531
532 /* Set smbus_block_read flag to identify in isr */
533 i2c->smbus_block_read = true;
534
535 /* Read byte from rx fifo and set message length */
536 rxmsg_len = xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
537
538 i2c->rx_msg->buf[i2c->rx_pos++] = rxmsg_len;
539
540 /* Check if received length is valid */
541 if (rxmsg_len <= I2C_SMBUS_BLOCK_MAX) {
542 /* Set Receive fifo depth */
543 if (rxmsg_len > IIC_RX_FIFO_DEPTH) {
544 /*
545 * When Rx msg len greater than or equal to Rx fifo capacity
546 * Receive fifo depth should set to Rx fifo capacity minus 1
547 */
548 rfd_set = IIC_RX_FIFO_DEPTH - 1;
549 i2c->rx_msg->len = rxmsg_len + 1;
550 } else if ((rxmsg_len == 1) ||
551 (rxmsg_len == 0)) {
552 /*
553 * Minimum of 3 bytes required to exit cleanly. 1 byte
554 * already received, Second byte is being received. Have
555 * to set NACK in read_rx before receiving the last byte
556 */
557 rfd_set = 0;
558 i2c->rx_msg->len = SMBUS_BLOCK_READ_MIN_LEN;
559 } else {
560 /*
561 * When Rx msg len less than Rx fifo capacity
562 * Receive fifo depth should set to Rx msg len minus 2
563 */
564 rfd_set = rxmsg_len - 2;
565 i2c->rx_msg->len = rxmsg_len + 1;
566 }
567 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set);
568
569 return;
570 }
571
572 /* Invalid message length, trigger STATE_ERROR with tx_msg_len in ISR */
573 i2c->tx_msg->len = 3;
574 i2c->smbus_block_read = false;
575 dev_err(i2c->adap.dev.parent, "smbus_block_read Invalid msg length\n");
576 }
577
xiic_read_rx(struct xiic_i2c * i2c)578 static void xiic_read_rx(struct xiic_i2c *i2c)
579 {
580 u8 bytes_in_fifo, cr = 0, bytes_to_read = 0;
581 u32 bytes_rem = 0;
582 int i;
583
584 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
585
586 if (!i2c->atomic)
587 dev_dbg(i2c->adap.dev.parent,
588 "%s entry, bytes in fifo: %d, rem: %d, SR: 0x%x, CR: 0x%x\n",
589 __func__, bytes_in_fifo, xiic_rx_space(i2c),
590 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
591 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
592
593 if (bytes_in_fifo > xiic_rx_space(i2c))
594 bytes_in_fifo = xiic_rx_space(i2c);
595
596 bytes_to_read = bytes_in_fifo;
597
598 if (!i2c->dynamic) {
599 bytes_rem = xiic_rx_space(i2c) - bytes_in_fifo;
600
601 /* Set msg length if smbus_block_read */
602 if (i2c->rx_msg->flags & I2C_M_RECV_LEN) {
603 xiic_smbus_block_read_setup(i2c);
604 return;
605 }
606
607 if (bytes_rem > IIC_RX_FIFO_DEPTH) {
608 bytes_to_read = bytes_in_fifo;
609 } else if (bytes_rem > 1) {
610 bytes_to_read = bytes_rem - 1;
611 } else if (bytes_rem == 1) {
612 bytes_to_read = 1;
613 /* Set NACK in CR to indicate slave transmitter */
614 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
615 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr |
616 XIIC_CR_NO_ACK_MASK);
617 } else if (bytes_rem == 0) {
618 bytes_to_read = bytes_in_fifo;
619
620 /* Generate stop on the bus if it is last message */
621 if (i2c->nmsgs == 1) {
622 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
623 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
624 ~XIIC_CR_MSMS_MASK);
625 }
626
627 /* Make TXACK=0, clean up for next transaction */
628 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
629 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
630 ~XIIC_CR_NO_ACK_MASK);
631 }
632 }
633
634 /* Read the fifo */
635 for (i = 0; i < bytes_to_read; i++) {
636 i2c->rx_msg->buf[i2c->rx_pos++] =
637 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
638 }
639
640 if (i2c->dynamic) {
641 u8 bytes;
642
643 /* Receive remaining bytes if less than fifo depth */
644 bytes = min_t(u8, xiic_rx_space(i2c), IIC_RX_FIFO_DEPTH);
645 bytes--;
646 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes);
647 }
648 }
649
xiic_error_check(struct xiic_i2c * i2c)650 static bool xiic_error_check(struct xiic_i2c *i2c)
651 {
652 bool status = false;
653 u32 pend, isr, ier;
654
655 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
656 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
657 pend = isr & ier;
658
659 if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
660 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
661 !(pend & XIIC_INTR_RX_FULL_MASK))) {
662 xiic_reinit(i2c);
663 status = true;
664 if (i2c->tx_msg || i2c->rx_msg)
665 i2c->atomic_xfer_state = STATE_ERROR;
666 }
667 return status;
668 }
669
xiic_tx_fifo_space(struct xiic_i2c * i2c)670 static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
671 {
672 /* return the actual space left in the FIFO */
673 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
674 }
675
xiic_fill_tx_fifo(struct xiic_i2c * i2c)676 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
677 {
678 u8 fifo_space = xiic_tx_fifo_space(i2c);
679 int len = xiic_tx_space(i2c);
680
681 len = (len > fifo_space) ? fifo_space : len;
682
683 if (!i2c->atomic)
684 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
685 __func__, len, fifo_space);
686
687 while (len--) {
688 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
689
690 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) {
691 /* last message in transfer -> STOP */
692 if (i2c->dynamic) {
693 data |= XIIC_TX_DYN_STOP_MASK;
694 } else {
695 u8 cr;
696 int status;
697
698 /* Wait till FIFO is empty so STOP is sent last */
699 status = xiic_wait_tx_empty(i2c);
700 if (status)
701 return;
702
703 /* Write to CR to stop */
704 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
705 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
706 ~XIIC_CR_MSMS_MASK);
707 }
708 if (!i2c->atomic)
709 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
710 }
711 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
712
713 if (i2c->atomic && xiic_error_check(i2c))
714 return;
715 }
716 }
717
xiic_wakeup(struct xiic_i2c * i2c,enum xilinx_i2c_state code)718 static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code)
719 {
720 i2c->tx_msg = NULL;
721 i2c->rx_msg = NULL;
722 i2c->nmsgs = 0;
723 i2c->state = code;
724 complete(&i2c->completion);
725 }
726
xiic_process(int irq,void * dev_id)727 static irqreturn_t xiic_process(int irq, void *dev_id)
728 {
729 struct xiic_i2c *i2c = dev_id;
730 u32 pend, isr, ier;
731 u32 clr = 0;
732 int xfer_more = 0;
733 int wakeup_req = 0;
734 enum xilinx_i2c_state wakeup_code = STATE_DONE;
735 int ret;
736
737 /* Get the interrupt Status from the IPIF. There is no clearing of
738 * interrupts in the IPIF. Interrupts must be cleared at the source.
739 * To find which interrupts are pending; AND interrupts pending with
740 * interrupts masked.
741 */
742 mutex_lock(&i2c->lock);
743 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
744 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
745 pend = isr & ier;
746
747 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
748 __func__, ier, isr, pend);
749 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
750 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
751 i2c->tx_msg, i2c->nmsgs);
752 dev_dbg(i2c->adap.dev.parent, "%s, ISR: 0x%x, CR: 0x%x\n",
753 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
754 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
755
756 /* Service requesting interrupt */
757 if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
758 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
759 !(pend & XIIC_INTR_RX_FULL_MASK))) {
760 /* bus arbritration lost, or...
761 * Transmit error _OR_ RX completed
762 * if this happens when RX_FULL is not set
763 * this is probably a TX error
764 */
765
766 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
767
768 /* dynamic mode seem to suffer from problems if we just flushes
769 * fifos and the next message is a TX with len 0 (only addr)
770 * reset the IP instead of just flush fifos
771 */
772 ret = xiic_reinit(i2c);
773 if (ret < 0)
774 dev_dbg(i2c->adap.dev.parent, "reinit failed\n");
775
776 if (i2c->rx_msg) {
777 wakeup_req = 1;
778 wakeup_code = STATE_ERROR;
779 }
780 if (i2c->tx_msg) {
781 wakeup_req = 1;
782 wakeup_code = STATE_ERROR;
783 }
784 /* don't try to handle other events */
785 goto out;
786 }
787 if (pend & XIIC_INTR_RX_FULL_MASK) {
788 /* Receive register/FIFO is full */
789
790 clr |= XIIC_INTR_RX_FULL_MASK;
791 if (!i2c->rx_msg) {
792 dev_dbg(i2c->adap.dev.parent,
793 "%s unexpected RX IRQ\n", __func__);
794 xiic_clear_rx_fifo(i2c);
795 goto out;
796 }
797
798 xiic_read_rx(i2c);
799 if (xiic_rx_space(i2c) == 0) {
800 /* this is the last part of the message */
801 i2c->rx_msg = NULL;
802
803 /* also clear TX error if there (RX complete) */
804 clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
805
806 dev_dbg(i2c->adap.dev.parent,
807 "%s end of message, nmsgs: %d\n",
808 __func__, i2c->nmsgs);
809
810 /* send next message if this wasn't the last,
811 * otherwise the transfer will be finialise when
812 * receiving the bus not busy interrupt
813 */
814 if (i2c->nmsgs > 1) {
815 i2c->nmsgs--;
816 i2c->tx_msg++;
817 dev_dbg(i2c->adap.dev.parent,
818 "%s will start next...\n", __func__);
819 xfer_more = 1;
820 }
821 }
822 }
823 if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
824 /* Transmit register/FIFO is empty or ½ empty */
825
826 clr |= (pend &
827 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK));
828
829 if (!i2c->tx_msg) {
830 dev_dbg(i2c->adap.dev.parent,
831 "%s unexpected TX IRQ\n", __func__);
832 goto out;
833 }
834
835 if (xiic_tx_space(i2c)) {
836 xiic_fill_tx_fifo(i2c);
837 } else {
838 /* current message fully written */
839 dev_dbg(i2c->adap.dev.parent,
840 "%s end of message sent, nmsgs: %d\n",
841 __func__, i2c->nmsgs);
842 /* Don't move onto the next message until the TX FIFO empties,
843 * to ensure that a NAK is not missed.
844 */
845 if (i2c->nmsgs > 1 && (pend & XIIC_INTR_TX_EMPTY_MASK)) {
846 i2c->nmsgs--;
847 i2c->tx_msg++;
848 xfer_more = 1;
849 } else {
850 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
851
852 dev_dbg(i2c->adap.dev.parent,
853 "%s Got TX IRQ but no more to do...\n",
854 __func__);
855 }
856 }
857 }
858
859 if (pend & XIIC_INTR_BNB_MASK) {
860 /* IIC bus has transitioned to not busy */
861 clr |= XIIC_INTR_BNB_MASK;
862
863 /* The bus is not busy, disable BusNotBusy interrupt */
864 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
865
866 if (i2c->tx_msg && i2c->smbus_block_read) {
867 i2c->smbus_block_read = false;
868 /* Set requested message len=1 to indicate STATE_DONE */
869 i2c->tx_msg->len = 1;
870 }
871
872 if (!i2c->tx_msg)
873 goto out;
874
875 wakeup_req = 1;
876
877 if (i2c->nmsgs == 1 && !i2c->rx_msg &&
878 xiic_tx_space(i2c) == 0)
879 wakeup_code = STATE_DONE;
880 else
881 wakeup_code = STATE_ERROR;
882 }
883
884 out:
885 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
886
887 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
888 if (xfer_more)
889 __xiic_start_xfer(i2c);
890 if (wakeup_req)
891 xiic_wakeup(i2c, wakeup_code);
892
893 WARN_ON(xfer_more && wakeup_req);
894
895 mutex_unlock(&i2c->lock);
896 return IRQ_HANDLED;
897 }
898
xiic_bus_busy(struct xiic_i2c * i2c)899 static int xiic_bus_busy(struct xiic_i2c *i2c)
900 {
901 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
902
903 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
904 }
905
xiic_wait_not_busy(struct xiic_i2c * i2c)906 static int xiic_wait_not_busy(struct xiic_i2c *i2c)
907 {
908 int tries = 3;
909 int err;
910
911 /* for instance if previous transfer was terminated due to TX error
912 * it might be that the bus is on it's way to become available
913 * give it at most 3 ms to wake
914 */
915 err = xiic_bus_busy(i2c);
916 while (err && tries--) {
917 if (i2c->atomic)
918 udelay(1000);
919 else
920 usleep_range(1000, 1100);
921 err = xiic_bus_busy(i2c);
922 }
923
924 return err;
925 }
926
xiic_recv_atomic(struct xiic_i2c * i2c)927 static void xiic_recv_atomic(struct xiic_i2c *i2c)
928 {
929 while (xiic_rx_space(i2c)) {
930 if (xiic_getreg32(i2c, XIIC_IISR_OFFSET) & XIIC_INTR_RX_FULL_MASK) {
931 xiic_read_rx(i2c);
932
933 /* Clear Rx full and Tx error interrupts. */
934 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK |
935 XIIC_INTR_TX_ERROR_MASK);
936 }
937 if (xiic_error_check(i2c))
938 return;
939 }
940
941 i2c->rx_msg = NULL;
942 xiic_irq_clr_en(i2c, XIIC_INTR_TX_ERROR_MASK);
943
944 /* send next message if this wasn't the last. */
945 if (i2c->nmsgs > 1) {
946 i2c->nmsgs--;
947 i2c->tx_msg++;
948 __xiic_start_xfer(i2c);
949 }
950 }
951
xiic_start_recv(struct xiic_i2c * i2c)952 static void xiic_start_recv(struct xiic_i2c *i2c)
953 {
954 u16 rx_watermark;
955 u8 cr = 0, rfd_set = 0;
956 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
957
958 if (!i2c->atomic)
959 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
960 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
961 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
962
963 /* Disable Tx interrupts */
964 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK);
965
966 if (i2c->dynamic) {
967 u8 bytes;
968 u16 val;
969
970 /* Clear and enable Rx full interrupt. */
971 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK |
972 XIIC_INTR_TX_ERROR_MASK);
973
974 /*
975 * We want to get all but last byte, because the TX_ERROR IRQ
976 * is used to indicate error ACK on the address, and
977 * negative ack on the last received byte, so to not mix
978 * them receive all but last.
979 * In the case where there is only one byte to receive
980 * we can check if ERROR and RX full is set at the same time
981 */
982 rx_watermark = msg->len;
983 bytes = min_t(u8, rx_watermark, IIC_RX_FIFO_DEPTH);
984
985 if (rx_watermark > 0)
986 bytes--;
987 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, bytes);
988
989 /* write the address */
990 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
991 i2c_8bit_addr_from_msg(msg) |
992 XIIC_TX_DYN_START_MASK);
993
994 /* If last message, include dynamic stop bit with length */
995 val = (i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0;
996 val |= msg->len;
997
998 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, val);
999
1000 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
1001 } else {
1002 /*
1003 * If previous message is Tx, make sure that Tx FIFO is empty
1004 * before starting a new transfer as the repeated start in
1005 * standard mode can corrupt the transaction if there are
1006 * still bytes to be transmitted in FIFO
1007 */
1008 if (i2c->prev_msg_tx) {
1009 int status;
1010
1011 status = xiic_wait_tx_empty(i2c);
1012 if (status)
1013 return;
1014 }
1015
1016 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1017
1018 /* Set Receive fifo depth */
1019 rx_watermark = msg->len;
1020 if (rx_watermark > IIC_RX_FIFO_DEPTH) {
1021 rfd_set = IIC_RX_FIFO_DEPTH - 1;
1022 } else if (rx_watermark == 1) {
1023 rfd_set = rx_watermark - 1;
1024
1025 /* Set No_ACK, except for smbus_block_read */
1026 if (!(i2c->rx_msg->flags & I2C_M_RECV_LEN)) {
1027 /* Handle single byte transfer separately */
1028 cr |= XIIC_CR_NO_ACK_MASK;
1029 }
1030 } else if (rx_watermark == 0) {
1031 rfd_set = rx_watermark;
1032 } else {
1033 rfd_set = rx_watermark - 2;
1034 }
1035 /* Check if RSTA should be set */
1036 if (cr & XIIC_CR_MSMS_MASK) {
1037 /* Already a master, RSTA should be set */
1038 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
1039 XIIC_CR_REPEATED_START_MASK) &
1040 ~(XIIC_CR_DIR_IS_TX_MASK));
1041 }
1042
1043 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rfd_set);
1044
1045 /* Clear and enable Rx full and transmit complete interrupts */
1046 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK |
1047 XIIC_INTR_TX_ERROR_MASK);
1048
1049 /* Write the address */
1050 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
1051 i2c_8bit_addr_from_msg(msg));
1052
1053 /* Write to Control Register,to start transaction in Rx mode */
1054 if ((cr & XIIC_CR_MSMS_MASK) == 0) {
1055 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
1056 XIIC_CR_MSMS_MASK)
1057 & ~(XIIC_CR_DIR_IS_TX_MASK));
1058 }
1059 if (!i2c->atomic)
1060 dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n",
1061 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
1062 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
1063 }
1064
1065 if (i2c->nmsgs == 1)
1066 /* very last, enable bus not busy as well */
1067 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
1068
1069 /* the message is tx:ed */
1070 i2c->tx_pos = msg->len;
1071
1072 i2c->prev_msg_tx = false;
1073
1074 /* Enable interrupts */
1075 if (!i2c->atomic)
1076 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
1077 else
1078 xiic_recv_atomic(i2c);
1079 }
1080
xiic_send_rem_atomic(struct xiic_i2c * i2c)1081 static void xiic_send_rem_atomic(struct xiic_i2c *i2c)
1082 {
1083 while (xiic_tx_space(i2c)) {
1084 if (xiic_tx_fifo_space(i2c)) {
1085 u16 data;
1086
1087 data = i2c->tx_msg->buf[i2c->tx_pos];
1088 i2c->tx_pos++;
1089 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) {
1090 /* last message in transfer -> STOP */
1091 if (i2c->dynamic) {
1092 data |= XIIC_TX_DYN_STOP_MASK;
1093 } else {
1094 u8 cr;
1095 int status;
1096
1097 /* Wait till FIFO is empty so STOP is sent last */
1098 status = xiic_wait_tx_empty(i2c);
1099 if (status)
1100 return;
1101
1102 /* Write to CR to stop */
1103 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1104 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &
1105 ~XIIC_CR_MSMS_MASK);
1106 }
1107 }
1108 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
1109 }
1110 if (xiic_error_check(i2c))
1111 return;
1112 }
1113
1114 if (i2c->nmsgs > 1) {
1115 i2c->nmsgs--;
1116 i2c->tx_msg++;
1117 __xiic_start_xfer(i2c);
1118 } else {
1119 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
1120 }
1121 }
1122
xiic_start_send(struct xiic_i2c * i2c)1123 static void xiic_start_send(struct xiic_i2c *i2c)
1124 {
1125 u8 cr = 0;
1126 u16 data;
1127 struct i2c_msg *msg = i2c->tx_msg;
1128
1129 if (!i2c->atomic) {
1130 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
1131 __func__, msg, msg->len);
1132 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
1133 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
1134 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
1135 }
1136
1137 if (i2c->dynamic) {
1138 /* write the address */
1139 data = i2c_8bit_addr_from_msg(msg) |
1140 XIIC_TX_DYN_START_MASK;
1141
1142 if (i2c->nmsgs == 1 && msg->len == 0)
1143 /* no data and last message -> add STOP */
1144 data |= XIIC_TX_DYN_STOP_MASK;
1145
1146 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
1147
1148 /* Clear any pending Tx empty, Tx Error and then enable them */
1149 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK |
1150 XIIC_INTR_TX_ERROR_MASK |
1151 XIIC_INTR_BNB_MASK |
1152 ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ?
1153 XIIC_INTR_TX_HALF_MASK : 0));
1154
1155 xiic_fill_tx_fifo(i2c);
1156 } else {
1157 /*
1158 * If previous message is Tx, make sure that Tx FIFO is empty
1159 * before starting a new transfer as the repeated start in
1160 * standard mode can corrupt the transaction if there are
1161 * still bytes to be transmitted in FIFO
1162 */
1163 if (i2c->prev_msg_tx) {
1164 int status;
1165
1166 status = xiic_wait_tx_empty(i2c);
1167 if (status)
1168 return;
1169 }
1170 /* Check if RSTA should be set */
1171 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1172 if (cr & XIIC_CR_MSMS_MASK) {
1173 /* Already a master, RSTA should be set */
1174 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, (cr |
1175 XIIC_CR_REPEATED_START_MASK |
1176 XIIC_CR_DIR_IS_TX_MASK) &
1177 ~(XIIC_CR_NO_ACK_MASK));
1178 }
1179
1180 /* Write address to FIFO */
1181 data = i2c_8bit_addr_from_msg(msg);
1182 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
1183
1184 /* Fill fifo */
1185 xiic_fill_tx_fifo(i2c);
1186
1187 if ((cr & XIIC_CR_MSMS_MASK) == 0) {
1188 /* Start Tx by writing to CR */
1189 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
1190 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr |
1191 XIIC_CR_MSMS_MASK |
1192 XIIC_CR_DIR_IS_TX_MASK);
1193 }
1194
1195 /* Clear any pending Tx empty, Tx Error and then enable them */
1196 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK |
1197 XIIC_INTR_TX_ERROR_MASK |
1198 XIIC_INTR_BNB_MASK);
1199 }
1200
1201 i2c->prev_msg_tx = true;
1202
1203 if (i2c->atomic && !i2c->atomic_xfer_state)
1204 xiic_send_rem_atomic(i2c);
1205 }
1206
__xiic_start_xfer(struct xiic_i2c * i2c)1207 static void __xiic_start_xfer(struct xiic_i2c *i2c)
1208 {
1209 int fifo_space = xiic_tx_fifo_space(i2c);
1210
1211 if (!i2c->atomic)
1212 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
1213 __func__, i2c->tx_msg, fifo_space);
1214
1215 if (!i2c->tx_msg)
1216 return;
1217
1218 if (i2c->atomic && xiic_error_check(i2c))
1219 return;
1220
1221 i2c->rx_pos = 0;
1222 i2c->tx_pos = 0;
1223 i2c->state = STATE_START;
1224 if (i2c->tx_msg->flags & I2C_M_RD) {
1225 /* we dont date putting several reads in the FIFO */
1226 xiic_start_recv(i2c);
1227 } else {
1228 xiic_start_send(i2c);
1229 }
1230 }
1231
xiic_start_xfer(struct xiic_i2c * i2c,struct i2c_msg * msgs,int num)1232 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num)
1233 {
1234 bool broken_read, max_read_len, smbus_blk_read;
1235 int ret, count;
1236
1237 if (i2c->atomic)
1238 spin_lock(&i2c->atomic_lock);
1239 else
1240 mutex_lock(&i2c->lock);
1241
1242 if (i2c->tx_msg || i2c->rx_msg) {
1243 dev_err(i2c->adap.dev.parent,
1244 "cannot start a transfer while busy\n");
1245 ret = -EBUSY;
1246 goto out;
1247 }
1248
1249 i2c->atomic_xfer_state = STATE_DONE;
1250
1251 /* In single master mode bus can only be busy, when in use by this
1252 * driver. If the register indicates bus being busy for some reason we
1253 * should ignore it, since bus will never be released and i2c will be
1254 * stuck forever.
1255 */
1256 if (!i2c->singlemaster) {
1257 ret = xiic_wait_not_busy(i2c);
1258 if (ret) {
1259 /* If the bus is stuck in a busy state, such as due to spurious low
1260 * pulses on the bus causing a false start condition to be detected,
1261 * then try to recover by re-initializing the controller and check
1262 * again if the bus is still busy.
1263 */
1264 dev_warn(i2c->adap.dev.parent, "I2C bus busy timeout, reinitializing\n");
1265 ret = xiic_reinit(i2c);
1266 if (ret)
1267 goto out;
1268 ret = xiic_wait_not_busy(i2c);
1269 if (ret)
1270 goto out;
1271 }
1272 }
1273
1274 i2c->tx_msg = msgs;
1275 i2c->rx_msg = NULL;
1276 i2c->nmsgs = num;
1277
1278 if (!i2c->atomic)
1279 init_completion(&i2c->completion);
1280
1281 /* Decide standard mode or Dynamic mode */
1282 i2c->dynamic = true;
1283
1284 /* Initialize prev message type */
1285 i2c->prev_msg_tx = false;
1286
1287 /*
1288 * Scan through nmsgs, use dynamic mode when none of the below three
1289 * conditions occur. We need standard mode even if one condition holds
1290 * true in the entire array of messages in a single transfer.
1291 * If read transaction as dynamic mode is broken for delayed reads
1292 * in xlnx,axi-iic-2.0 / xlnx,xps-iic-2.00.a IP versions.
1293 * If read length is > 255 bytes.
1294 * If smbus_block_read transaction.
1295 */
1296 for (count = 0; count < i2c->nmsgs; count++) {
1297 broken_read = (i2c->quirks & DYNAMIC_MODE_READ_BROKEN_BIT) &&
1298 (i2c->tx_msg[count].flags & I2C_M_RD);
1299 max_read_len = (i2c->tx_msg[count].flags & I2C_M_RD) &&
1300 (i2c->tx_msg[count].len > MAX_READ_LENGTH_DYNAMIC);
1301 smbus_blk_read = (i2c->tx_msg[count].flags & I2C_M_RECV_LEN);
1302
1303 if (broken_read || max_read_len || smbus_blk_read) {
1304 i2c->dynamic = false;
1305 break;
1306 }
1307 }
1308
1309 ret = xiic_reinit(i2c);
1310 if (!ret)
1311 __xiic_start_xfer(i2c);
1312
1313 out:
1314 if (i2c->atomic)
1315 spin_unlock(&i2c->atomic_lock);
1316 else
1317 mutex_unlock(&i2c->lock);
1318
1319 return ret;
1320 }
1321
xiic_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)1322 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
1323 {
1324 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
1325 int err;
1326
1327 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
1328 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
1329
1330 err = pm_runtime_resume_and_get(i2c->dev);
1331 if (err < 0)
1332 return err;
1333
1334 err = xiic_start_xfer(i2c, msgs, num);
1335 if (err < 0)
1336 goto out;
1337
1338 err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT);
1339 mutex_lock(&i2c->lock);
1340 if (err == 0) { /* Timeout */
1341 i2c->tx_msg = NULL;
1342 i2c->rx_msg = NULL;
1343 i2c->nmsgs = 0;
1344 err = -ETIMEDOUT;
1345 } else {
1346 err = (i2c->state == STATE_DONE) ? num : -EIO;
1347 }
1348 mutex_unlock(&i2c->lock);
1349
1350 out:
1351 pm_runtime_put_autosuspend(i2c->dev);
1352 return err;
1353 }
1354
xiic_xfer_atomic(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)1355 static int xiic_xfer_atomic(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
1356 {
1357 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
1358 u32 status_reg;
1359 int err;
1360
1361 err = xiic_i2c_runtime_resume(i2c->dev);
1362 if (err)
1363 return err;
1364
1365 i2c->atomic = true;
1366 err = xiic_start_xfer(i2c, msgs, num);
1367 if (err < 0)
1368 return err;
1369
1370 err = readl_poll_timeout_atomic(i2c->base + XIIC_SR_REG_OFFSET,
1371 status_reg, !(status_reg & XIIC_SR_BUS_BUSY_MASK),
1372 1, XIIC_XFER_TIMEOUT_US);
1373
1374 if (err) /* Timeout */
1375 err = -ETIMEDOUT;
1376
1377 spin_lock(&i2c->atomic_lock);
1378 if (err || i2c->state) {
1379 i2c->tx_msg = NULL;
1380 i2c->rx_msg = NULL;
1381 i2c->nmsgs = 0;
1382 }
1383
1384 err = (i2c->atomic_xfer_state == STATE_DONE) ? num : -EIO;
1385 spin_unlock(&i2c->atomic_lock);
1386
1387 i2c->atomic = false;
1388 xiic_i2c_runtime_suspend(i2c->dev);
1389
1390 return err;
1391 }
1392
xiic_func(struct i2c_adapter * adap)1393 static u32 xiic_func(struct i2c_adapter *adap)
1394 {
1395 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
1396 }
1397
1398 static const struct i2c_algorithm xiic_algorithm = {
1399 .xfer = xiic_xfer,
1400 .xfer_atomic = xiic_xfer_atomic,
1401 .functionality = xiic_func,
1402 };
1403
1404 static const struct i2c_adapter xiic_adapter = {
1405 .owner = THIS_MODULE,
1406 .class = I2C_CLASS_DEPRECATED,
1407 .algo = &xiic_algorithm,
1408 };
1409
1410 static const struct xiic_version_data xiic_2_00 = {
1411 .quirks = DYNAMIC_MODE_READ_BROKEN_BIT,
1412 };
1413
1414 static const struct of_device_id xiic_of_match[] = {
1415 { .compatible = "xlnx,xps-iic-2.00.a", .data = &xiic_2_00 },
1416 { .compatible = "xlnx,axi-iic-2.1", },
1417 {},
1418 };
1419 MODULE_DEVICE_TABLE(of, xiic_of_match);
1420
xiic_i2c_probe(struct platform_device * pdev)1421 static int xiic_i2c_probe(struct platform_device *pdev)
1422 {
1423 struct device *dev = &pdev->dev;
1424 struct fwnode_handle *fwnode = dev_fwnode(dev);
1425 struct xiic_i2c *i2c;
1426 struct xiic_i2c_platform_data *pdata;
1427 const struct xiic_version_data *data;
1428 struct resource *res;
1429 int ret, irq;
1430 u8 i;
1431 u32 sr;
1432
1433 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
1434 if (!i2c)
1435 return -ENOMEM;
1436
1437 data = device_get_match_data(dev);
1438 if (data)
1439 i2c->quirks = data->quirks;
1440
1441 i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1442 if (IS_ERR(i2c->base))
1443 return PTR_ERR(i2c->base);
1444
1445 irq = platform_get_irq(pdev, 0);
1446 if (irq < 0)
1447 return irq;
1448
1449 pdata = dev_get_platdata(dev);
1450
1451 /* hook up driver to tree */
1452 platform_set_drvdata(pdev, i2c);
1453 i2c->adap = xiic_adapter;
1454 i2c->adap.nr = pdev->id;
1455 i2c_set_adapdata(&i2c->adap, i2c);
1456 i2c->adap.dev.parent = &pdev->dev;
1457 device_set_node(&i2c->adap.dev, fwnode);
1458 snprintf(i2c->adap.name, sizeof(i2c->adap.name),
1459 DRIVER_NAME " %s", pdev->name);
1460
1461 ret = devm_mutex_init(dev, &i2c->lock);
1462 if (ret)
1463 return ret;
1464
1465 spin_lock_init(&i2c->atomic_lock);
1466
1467 if (is_of_node(fwnode)) {
1468 i2c->clk = devm_clk_get_enabled(dev, NULL);
1469 if (IS_ERR(i2c->clk))
1470 return dev_err_probe(dev, PTR_ERR(i2c->clk),
1471 "failed to enable input clock.\n");
1472 }
1473
1474 i2c->dev = dev;
1475
1476 pm_runtime_set_autosuspend_delay(dev, XIIC_PM_TIMEOUT);
1477 pm_runtime_use_autosuspend(dev);
1478 ret = devm_pm_runtime_set_active_enabled(dev);
1479 if (ret)
1480 return ret;
1481
1482 /* SCL frequency configuration */
1483 i2c->input_clk = clk_get_rate(i2c->clk);
1484 ret = device_property_read_u32(dev, "clock-frequency", &i2c->i2c_clk);
1485 /* If clock-frequency not specified in DT, do not configure in SW */
1486 if (ret || i2c->i2c_clk > I2C_MAX_FAST_MODE_PLUS_FREQ)
1487 i2c->i2c_clk = 0;
1488
1489 ret = devm_request_threaded_irq(dev, irq, NULL, xiic_process,
1490 IRQF_ONESHOT, pdev->name, i2c);
1491 if (ret)
1492 return ret;
1493
1494 i2c->singlemaster = device_property_read_bool(dev, "single-master");
1495
1496 /*
1497 * Detect endianness
1498 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not
1499 * set, assume that the endianness was wrong and swap.
1500 */
1501 i2c->endianness = LITTLE;
1502 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
1503 /* Reset is cleared in xiic_reinit */
1504 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET);
1505 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK))
1506 i2c->endianness = BIG;
1507
1508 ret = xiic_reinit(i2c);
1509 if (ret)
1510 return dev_err_probe(dev, ret, "Cannot xiic_reinit\n");
1511
1512 /* add i2c adapter to i2c tree */
1513 ret = i2c_add_numbered_adapter(&i2c->adap);
1514 if (ret) {
1515 xiic_deinit(i2c);
1516 return ret;
1517 }
1518
1519 if (pdata) {
1520 /* add in known devices to the bus */
1521 for (i = 0; i < pdata->num_devices; i++)
1522 i2c_new_client_device(&i2c->adap, pdata->devices + i);
1523 }
1524
1525 dev_dbg(dev, "mmio %pR irq %d scl clock frequency %d\n",
1526 res, irq, i2c->i2c_clk);
1527
1528 return 0;
1529 }
1530
xiic_i2c_remove(struct platform_device * pdev)1531 static void xiic_i2c_remove(struct platform_device *pdev)
1532 {
1533 struct device *dev = &pdev->dev;
1534 struct xiic_i2c *i2c = platform_get_drvdata(pdev);
1535 int ret;
1536
1537 /* remove adapter & data */
1538 i2c_del_adapter(&i2c->adap);
1539
1540 ret = pm_runtime_get_sync(dev);
1541 if (ret < 0)
1542 dev_warn(dev, "Failed to activate device for removal (%pe)\n",
1543 ERR_PTR(ret));
1544 else
1545 xiic_deinit(i2c);
1546
1547 pm_runtime_put_sync(dev);
1548 }
1549
1550 static const struct dev_pm_ops xiic_dev_pm_ops = {
1551 SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend,
1552 xiic_i2c_runtime_resume, NULL)
1553 };
1554
1555 static struct platform_driver xiic_i2c_driver = {
1556 .probe = xiic_i2c_probe,
1557 .remove = xiic_i2c_remove,
1558 .driver = {
1559 .name = DRIVER_NAME,
1560 .of_match_table = of_match_ptr(xiic_of_match),
1561 .pm = &xiic_dev_pm_ops,
1562 },
1563 };
1564
1565 module_platform_driver(xiic_i2c_driver);
1566
1567 MODULE_ALIAS("platform:" DRIVER_NAME);
1568 MODULE_AUTHOR("info@mocean-labs.com");
1569 MODULE_DESCRIPTION("Xilinx I2C bus driver");
1570 MODULE_LICENSE("GPL v2");
1571