1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * I3C Controller driver
4 * Copyright 2025 Analog Devices Inc.
5 * Author: Jorge Marques <jorge.marques@analog.com>
6 */
7
8 #include <linux/bitops.h>
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/err.h>
12 #include <linux/errno.h>
13 #include <linux/adi-axi-common.h>
14 #include <linux/i3c/master.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/platform_device.h>
20
21 #include "../internals.h"
22
23 #define ADI_MAX_DEVS 16
24 #define ADI_HAS_MDB_FROM_BCR(x) (FIELD_GET(BIT(2), (x)))
25
26 #define REG_ENABLE 0x040
27
28 #define REG_PID_L 0x054
29 #define REG_PID_H 0x058
30 #define REG_DCR_BCR_DA 0x05c
31 #define REG_DCR_BCR_DA_GET_DA(x) FIELD_GET(GENMASK(22, 16), (x))
32 #define REG_DCR_BCR_DA_GET_BCR(x) FIELD_GET(GENMASK(15, 8), (x))
33 #define REG_DCR_BCR_DA_GET_DCR(x) FIELD_GET(GENMASK(7, 0), (x))
34
35 #define REG_IRQ_MASK 0x080
36 #define REG_IRQ_PENDING 0x084
37 #define REG_IRQ_PENDING_DAA BIT(7)
38 #define REG_IRQ_PENDING_IBI BIT(6)
39 #define REG_IRQ_PENDING_CMDR BIT(5)
40
41 #define REG_CMD_FIFO 0x0d4
42 #define REG_CMD_FIFO_0_IS_CCC BIT(22)
43 #define REG_CMD_FIFO_0_BCAST BIT(21)
44 #define REG_CMD_FIFO_0_SR BIT(20)
45 #define REG_CMD_FIFO_0_LEN(l) FIELD_PREP(GENMASK(19, 8), (l))
46 #define REG_CMD_FIFO_0_DEV_ADDR(a) FIELD_PREP(GENMASK(7, 1), (a))
47 #define REG_CMD_FIFO_0_RNW BIT(0)
48 #define REG_CMD_FIFO_1_CCC(id) FIELD_PREP(GENMASK(7, 0), (id))
49
50 #define REG_CMD_FIFO_ROOM 0x0c0
51 #define REG_CMDR_FIFO 0x0d8
52 #define REG_CMDR_FIFO_UDA_ERROR 8
53 #define REG_CMDR_FIFO_NACK_RESP 6
54 #define REG_CMDR_FIFO_CE2_ERROR 4
55 #define REG_CMDR_FIFO_CE0_ERROR 1
56 #define REG_CMDR_FIFO_NO_ERROR 0
57 #define REG_CMDR_FIFO_ERROR(x) FIELD_GET(GENMASK(23, 20), (x))
58 #define REG_CMDR_FIFO_XFER_BYTES(x) FIELD_GET(GENMASK(19, 8), (x))
59
60 #define REG_SDO_FIFO 0x0dc
61 #define REG_SDO_FIFO_ROOM 0x0c8
62 #define REG_SDI_FIFO 0x0e0
63 #define REG_IBI_FIFO 0x0e4
64 #define REG_FIFO_STATUS 0x0e8
65 #define REG_FIFO_STATUS_CMDR_EMPTY BIT(0)
66 #define REG_FIFO_STATUS_IBI_EMPTY BIT(1)
67
68 #define REG_OPS 0x100
69 #define REG_OPS_PP_SG_MASK GENMASK(6, 5)
70 #define REG_OPS_SET_SG(x) FIELD_PREP(REG_OPS_PP_SG_MASK, (x))
71
72 #define REG_IBI_CONFIG 0x140
73 #define REG_IBI_CONFIG_ENABLE BIT(0)
74 #define REG_IBI_CONFIG_LISTEN BIT(1)
75
76 #define REG_DEV_CHAR 0x180
77 #define REG_DEV_CHAR_IS_I2C BIT(0)
78 #define REG_DEV_CHAR_IS_ATTACHED BIT(1)
79 #define REG_DEV_CHAR_BCR_IBI(x) FIELD_PREP(GENMASK(3, 2), (x))
80 #define REG_DEV_CHAR_WEN BIT(8)
81 #define REG_DEV_CHAR_ADDR(x) FIELD_PREP(GENMASK(15, 9), (x))
82
83 enum speed_grade {PP_SG_UNSET, PP_SG_1MHZ, PP_SG_3MHZ, PP_SG_6MHZ, PP_SG_12MHZ};
84
85 struct adi_i3c_cmd {
86 u32 cmd0;
87 u32 cmd1;
88 u32 tx_len;
89 const void *tx_buf;
90 u32 rx_len;
91 void *rx_buf;
92 u32 error;
93 };
94
95 struct adi_i3c_xfer {
96 struct list_head node;
97 struct completion comp;
98 int ret;
99 unsigned int ncmds;
100 unsigned int ncmds_comp;
101 struct adi_i3c_cmd cmds[] __counted_by(ncmds);
102 };
103
104 struct adi_i3c_master {
105 struct i3c_master_controller base;
106 u32 free_rr_slots;
107 struct {
108 unsigned int num_slots;
109 struct i3c_dev_desc **slots;
110 spinlock_t lock; /* Protect IBI slot access */
111 } ibi;
112 struct {
113 struct list_head list;
114 struct adi_i3c_xfer *cur;
115 spinlock_t lock; /* Protect transfer */
116 } xferqueue;
117 void __iomem *regs;
118 struct clk *clk;
119 unsigned long i3c_scl_lim;
120 struct {
121 u8 addrs[ADI_MAX_DEVS];
122 u8 index;
123 } daa;
124 };
125
to_adi_i3c_master(struct i3c_master_controller * master)126 static inline struct adi_i3c_master *to_adi_i3c_master(struct i3c_master_controller *master)
127 {
128 return container_of(master, struct adi_i3c_master, base);
129 }
130
adi_i3c_master_wr_to_tx_fifo(struct adi_i3c_master * master,const u8 * buf,unsigned int nbytes)131 static void adi_i3c_master_wr_to_tx_fifo(struct adi_i3c_master *master,
132 const u8 *buf, unsigned int nbytes)
133 {
134 unsigned int n, m;
135
136 n = readl(master->regs + REG_SDO_FIFO_ROOM);
137 m = min(n, nbytes);
138 i3c_writel_fifo(master->regs + REG_SDO_FIFO, buf, m);
139 }
140
adi_i3c_master_rd_from_rx_fifo(struct adi_i3c_master * master,u8 * buf,unsigned int nbytes)141 static void adi_i3c_master_rd_from_rx_fifo(struct adi_i3c_master *master,
142 u8 *buf, unsigned int nbytes)
143 {
144 i3c_readl_fifo(master->regs + REG_SDI_FIFO, buf, nbytes);
145 }
146
adi_i3c_master_supports_ccc_cmd(struct i3c_master_controller * m,const struct i3c_ccc_cmd * cmd)147 static bool adi_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m,
148 const struct i3c_ccc_cmd *cmd)
149 {
150 if (cmd->ndests > 1)
151 return false;
152
153 switch (cmd->id) {
154 case I3C_CCC_ENEC(true):
155 case I3C_CCC_ENEC(false):
156 case I3C_CCC_DISEC(true):
157 case I3C_CCC_DISEC(false):
158 case I3C_CCC_RSTDAA(true):
159 case I3C_CCC_RSTDAA(false):
160 case I3C_CCC_ENTDAA:
161 case I3C_CCC_SETDASA:
162 case I3C_CCC_SETNEWDA:
163 case I3C_CCC_GETMWL:
164 case I3C_CCC_GETMRL:
165 case I3C_CCC_GETPID:
166 case I3C_CCC_GETBCR:
167 case I3C_CCC_GETDCR:
168 case I3C_CCC_GETSTATUS:
169 case I3C_CCC_GETHDRCAP:
170 return true;
171 default:
172 break;
173 }
174
175 return false;
176 }
177
adi_i3c_master_disable(struct adi_i3c_master * master)178 static int adi_i3c_master_disable(struct adi_i3c_master *master)
179 {
180 writel(0, master->regs + REG_IBI_CONFIG);
181
182 return 0;
183 }
184
adi_i3c_master_alloc_xfer(struct adi_i3c_master * master,unsigned int ncmds)185 static struct adi_i3c_xfer *adi_i3c_master_alloc_xfer(struct adi_i3c_master *master,
186 unsigned int ncmds)
187 {
188 struct adi_i3c_xfer *xfer;
189
190 xfer = kzalloc_flex(*xfer, cmds, ncmds);
191 if (!xfer)
192 return NULL;
193
194 INIT_LIST_HEAD(&xfer->node);
195 xfer->ncmds = ncmds;
196 xfer->ret = -ETIMEDOUT;
197
198 return xfer;
199 }
200
adi_i3c_master_start_xfer_locked(struct adi_i3c_master * master)201 static void adi_i3c_master_start_xfer_locked(struct adi_i3c_master *master)
202 {
203 struct adi_i3c_xfer *xfer = master->xferqueue.cur;
204 unsigned int i, n, m;
205
206 if (!xfer)
207 return;
208
209 for (i = 0; i < xfer->ncmds; i++) {
210 struct adi_i3c_cmd *cmd = &xfer->cmds[i];
211
212 if (!(cmd->cmd0 & REG_CMD_FIFO_0_RNW))
213 adi_i3c_master_wr_to_tx_fifo(master, cmd->tx_buf, cmd->tx_len);
214 }
215
216 n = readl(master->regs + REG_CMD_FIFO_ROOM);
217 for (i = 0; i < xfer->ncmds; i++) {
218 struct adi_i3c_cmd *cmd = &xfer->cmds[i];
219
220 m = cmd->cmd0 & REG_CMD_FIFO_0_IS_CCC ? 2 : 1;
221 if (m > n)
222 break;
223 writel(cmd->cmd0, master->regs + REG_CMD_FIFO);
224 if (cmd->cmd0 & REG_CMD_FIFO_0_IS_CCC)
225 writel(cmd->cmd1, master->regs + REG_CMD_FIFO);
226 n -= m;
227 }
228 }
229
adi_i3c_master_end_xfer_locked(struct adi_i3c_master * master,u32 pending)230 static void adi_i3c_master_end_xfer_locked(struct adi_i3c_master *master,
231 u32 pending)
232 {
233 struct adi_i3c_xfer *xfer = master->xferqueue.cur;
234 int i, ret = 0;
235
236 if (!xfer)
237 return;
238
239 while (!(readl(master->regs + REG_FIFO_STATUS) & REG_FIFO_STATUS_CMDR_EMPTY)) {
240 struct adi_i3c_cmd *cmd;
241 u32 cmdr, rx_len;
242
243 cmdr = readl(master->regs + REG_CMDR_FIFO);
244
245 cmd = &xfer->cmds[xfer->ncmds_comp++];
246 if (cmd->cmd0 & REG_CMD_FIFO_0_RNW) {
247 rx_len = min_t(u32, REG_CMDR_FIFO_XFER_BYTES(cmdr), cmd->rx_len);
248 adi_i3c_master_rd_from_rx_fifo(master, cmd->rx_buf, rx_len);
249 }
250 cmd->error = REG_CMDR_FIFO_ERROR(cmdr);
251 }
252
253 for (i = 0; i < xfer->ncmds_comp; i++) {
254 switch (xfer->cmds[i].error) {
255 case REG_CMDR_FIFO_NO_ERROR:
256 break;
257
258 case REG_CMDR_FIFO_CE0_ERROR:
259 case REG_CMDR_FIFO_CE2_ERROR:
260 case REG_CMDR_FIFO_NACK_RESP:
261 case REG_CMDR_FIFO_UDA_ERROR:
262 ret = -EIO;
263 break;
264
265 default:
266 ret = -EINVAL;
267 break;
268 }
269 }
270
271 xfer->ret = ret;
272
273 if (xfer->ncmds_comp != xfer->ncmds)
274 return;
275
276 complete(&xfer->comp);
277
278 xfer = list_first_entry_or_null(&master->xferqueue.list,
279 struct adi_i3c_xfer, node);
280 if (xfer)
281 list_del_init(&xfer->node);
282
283 master->xferqueue.cur = xfer;
284 adi_i3c_master_start_xfer_locked(master);
285 }
286
adi_i3c_master_queue_xfer(struct adi_i3c_master * master,struct adi_i3c_xfer * xfer)287 static void adi_i3c_master_queue_xfer(struct adi_i3c_master *master,
288 struct adi_i3c_xfer *xfer)
289 {
290 init_completion(&xfer->comp);
291 guard(spinlock_irqsave)(&master->xferqueue.lock);
292 if (master->xferqueue.cur) {
293 list_add_tail(&xfer->node, &master->xferqueue.list);
294 } else {
295 master->xferqueue.cur = xfer;
296 adi_i3c_master_start_xfer_locked(master);
297 }
298 }
299
adi_i3c_master_unqueue_xfer(struct adi_i3c_master * master,struct adi_i3c_xfer * xfer)300 static void adi_i3c_master_unqueue_xfer(struct adi_i3c_master *master,
301 struct adi_i3c_xfer *xfer)
302 {
303 guard(spinlock_irqsave)(&master->xferqueue.lock);
304 if (master->xferqueue.cur == xfer)
305 master->xferqueue.cur = NULL;
306 else
307 list_del_init(&xfer->node);
308
309 writel(0x01, master->regs + REG_ENABLE);
310 writel(0x00, master->regs + REG_ENABLE);
311 writel(REG_IRQ_PENDING_CMDR, master->regs + REG_IRQ_MASK);
312 }
313
adi_i3c_cmd_get_err(struct adi_i3c_cmd * cmd)314 static enum i3c_error_code adi_i3c_cmd_get_err(struct adi_i3c_cmd *cmd)
315 {
316 switch (cmd->error) {
317 case REG_CMDR_FIFO_CE0_ERROR:
318 return I3C_ERROR_M0;
319
320 case REG_CMDR_FIFO_CE2_ERROR:
321 case REG_CMDR_FIFO_NACK_RESP:
322 return I3C_ERROR_M2;
323
324 default:
325 break;
326 }
327
328 return I3C_ERROR_UNKNOWN;
329 }
330
adi_i3c_master_send_ccc_cmd(struct i3c_master_controller * m,struct i3c_ccc_cmd * cmd)331 static int adi_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
332 struct i3c_ccc_cmd *cmd)
333 {
334 struct adi_i3c_master *master = to_adi_i3c_master(m);
335 struct adi_i3c_cmd *ccmd;
336
337 struct adi_i3c_xfer *xfer __free(kfree) = adi_i3c_master_alloc_xfer(master, 1);
338 if (!xfer)
339 return -ENOMEM;
340
341 ccmd = xfer->cmds;
342 ccmd->cmd1 = REG_CMD_FIFO_1_CCC(cmd->id);
343 ccmd->cmd0 = REG_CMD_FIFO_0_IS_CCC |
344 REG_CMD_FIFO_0_LEN(cmd->dests[0].payload.len);
345
346 if (cmd->id & I3C_CCC_DIRECT)
347 ccmd->cmd0 |= REG_CMD_FIFO_0_DEV_ADDR(cmd->dests[0].addr);
348
349 if (cmd->rnw) {
350 ccmd->cmd0 |= REG_CMD_FIFO_0_RNW;
351 ccmd->rx_buf = cmd->dests[0].payload.data;
352 ccmd->rx_len = cmd->dests[0].payload.len;
353 } else {
354 ccmd->tx_buf = cmd->dests[0].payload.data;
355 ccmd->tx_len = cmd->dests[0].payload.len;
356 }
357
358 adi_i3c_master_queue_xfer(master, xfer);
359 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
360 adi_i3c_master_unqueue_xfer(master, xfer);
361
362 cmd->err = adi_i3c_cmd_get_err(&xfer->cmds[0]);
363
364 return xfer->ret;
365 }
366
adi_i3c_master_i3c_xfers(struct i3c_dev_desc * dev,struct i3c_xfer * xfers,int nxfers,enum i3c_xfer_mode mode)367 static int adi_i3c_master_i3c_xfers(struct i3c_dev_desc *dev,
368 struct i3c_xfer *xfers,
369 int nxfers, enum i3c_xfer_mode mode)
370 {
371 struct i3c_master_controller *m = i3c_dev_get_master(dev);
372 struct adi_i3c_master *master = to_adi_i3c_master(m);
373 int i, ret;
374
375 if (!nxfers)
376 return 0;
377
378 struct adi_i3c_xfer *xfer __free(kfree) = adi_i3c_master_alloc_xfer(master, nxfers);
379 if (!xfer)
380 return -ENOMEM;
381
382 for (i = 0; i < nxfers; i++) {
383 struct adi_i3c_cmd *ccmd = &xfer->cmds[i];
384
385 ccmd->cmd0 = REG_CMD_FIFO_0_DEV_ADDR(dev->info.dyn_addr);
386
387 if (xfers[i].rnw) {
388 ccmd->cmd0 |= REG_CMD_FIFO_0_RNW;
389 ccmd->rx_buf = xfers[i].data.in;
390 ccmd->rx_len = xfers[i].len;
391 } else {
392 ccmd->tx_buf = xfers[i].data.out;
393 ccmd->tx_len = xfers[i].len;
394 }
395
396 ccmd->cmd0 |= REG_CMD_FIFO_0_LEN(xfers[i].len);
397
398 if (i < nxfers - 1)
399 ccmd->cmd0 |= REG_CMD_FIFO_0_SR;
400
401 if (!i)
402 ccmd->cmd0 |= REG_CMD_FIFO_0_BCAST;
403 }
404
405 adi_i3c_master_queue_xfer(master, xfer);
406 if (!wait_for_completion_timeout(&xfer->comp,
407 msecs_to_jiffies(1000)))
408 adi_i3c_master_unqueue_xfer(master, xfer);
409
410 ret = xfer->ret;
411
412 for (i = 0; i < nxfers; i++)
413 xfers[i].err = adi_i3c_cmd_get_err(&xfer->cmds[i]);
414
415 return ret;
416 }
417
418 struct adi_i3c_i2c_dev_data {
419 struct i3c_generic_ibi_pool *ibi_pool;
420 u16 id;
421 s16 ibi;
422 };
423
adi_i3c_master_get_rr_slot(struct adi_i3c_master * master,u8 dyn_addr)424 static int adi_i3c_master_get_rr_slot(struct adi_i3c_master *master,
425 u8 dyn_addr)
426 {
427 if (!master->free_rr_slots)
428 return -ENOSPC;
429
430 return ffs(master->free_rr_slots) - 1;
431 }
432
adi_i3c_master_reattach_i3c_dev(struct i3c_dev_desc * dev,u8 dyn_addr)433 static int adi_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, u8 dyn_addr)
434 {
435 struct i3c_master_controller *m = i3c_dev_get_master(dev);
436 struct adi_i3c_master *master = to_adi_i3c_master(m);
437 u8 addr;
438
439 addr = dev->info.dyn_addr ? dev->info.dyn_addr : dev->info.static_addr;
440
441 writel(REG_DEV_CHAR_ADDR(dyn_addr), master->regs + REG_DEV_CHAR);
442 writel((readl(master->regs + REG_DEV_CHAR) &
443 ~REG_DEV_CHAR_IS_ATTACHED) | REG_DEV_CHAR_WEN,
444 master->regs + REG_DEV_CHAR);
445
446 writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR);
447 writel(readl(master->regs + REG_DEV_CHAR) |
448 REG_DEV_CHAR_IS_ATTACHED | REG_DEV_CHAR_WEN,
449 master->regs + REG_DEV_CHAR);
450
451 return 0;
452 }
453
adi_i3c_master_attach_i3c_dev(struct i3c_dev_desc * dev)454 static int adi_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
455 {
456 struct i3c_master_controller *m = i3c_dev_get_master(dev);
457 struct adi_i3c_master *master = to_adi_i3c_master(m);
458 struct adi_i3c_i2c_dev_data *data;
459 int slot;
460 u8 addr;
461
462 data = kzalloc_obj(*data);
463 if (!data)
464 return -ENOMEM;
465
466 slot = adi_i3c_master_get_rr_slot(master, dev->info.dyn_addr);
467 if (slot < 0) {
468 kfree(data);
469 return slot;
470 }
471
472 data->id = slot;
473 i3c_dev_set_master_data(dev, data);
474 master->free_rr_slots &= ~BIT(slot);
475
476 addr = dev->info.dyn_addr ? dev->info.dyn_addr : dev->info.static_addr;
477
478 writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR);
479 writel(readl(master->regs + REG_DEV_CHAR) |
480 REG_DEV_CHAR_IS_ATTACHED | REG_DEV_CHAR_WEN,
481 master->regs + REG_DEV_CHAR);
482
483 return 0;
484 }
485
adi_i3c_master_sync_dev_char(struct i3c_master_controller * m)486 static void adi_i3c_master_sync_dev_char(struct i3c_master_controller *m)
487 {
488 struct adi_i3c_master *master = to_adi_i3c_master(m);
489 struct i3c_dev_desc *i3cdev;
490 u32 bcr_ibi;
491 u8 addr;
492
493 i3c_bus_for_each_i3cdev(&m->bus, i3cdev) {
494 addr = i3cdev->info.dyn_addr ?
495 i3cdev->info.dyn_addr : i3cdev->info.static_addr;
496 writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR);
497 bcr_ibi = FIELD_GET(I3C_BCR_IBI_PAYLOAD | I3C_BCR_IBI_REQ_CAP, (i3cdev->info.bcr));
498 writel(readl(master->regs + REG_DEV_CHAR) |
499 REG_DEV_CHAR_BCR_IBI(bcr_ibi) | REG_DEV_CHAR_WEN,
500 master->regs + REG_DEV_CHAR);
501 }
502 }
503
adi_i3c_master_detach_i3c_dev(struct i3c_dev_desc * dev)504 static void adi_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
505 {
506 struct i3c_master_controller *m = i3c_dev_get_master(dev);
507 struct adi_i3c_master *master = to_adi_i3c_master(m);
508 struct adi_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
509 u8 addr;
510
511 addr = dev->info.dyn_addr ? dev->info.dyn_addr : dev->info.static_addr;
512
513 writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR);
514 writel((readl(master->regs + REG_DEV_CHAR) &
515 ~REG_DEV_CHAR_IS_ATTACHED) | REG_DEV_CHAR_WEN,
516 master->regs + REG_DEV_CHAR);
517
518 i3c_dev_set_master_data(dev, NULL);
519 master->free_rr_slots |= BIT(data->id);
520 kfree(data);
521 }
522
adi_i3c_master_attach_i2c_dev(struct i2c_dev_desc * dev)523 static int adi_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev)
524 {
525 struct i3c_master_controller *m = i2c_dev_get_master(dev);
526 struct adi_i3c_master *master = to_adi_i3c_master(m);
527 struct adi_i3c_i2c_dev_data *data;
528 int slot;
529
530 slot = adi_i3c_master_get_rr_slot(master, 0);
531 if (slot < 0)
532 return slot;
533
534 data = kzalloc_obj(*data);
535 if (!data)
536 return -ENOMEM;
537
538 data->id = slot;
539 master->free_rr_slots &= ~BIT(slot);
540 i2c_dev_set_master_data(dev, data);
541
542 writel(REG_DEV_CHAR_ADDR(dev->addr) |
543 REG_DEV_CHAR_IS_I2C | REG_DEV_CHAR_IS_ATTACHED | REG_DEV_CHAR_WEN,
544 master->regs + REG_DEV_CHAR);
545
546 return 0;
547 }
548
adi_i3c_master_detach_i2c_dev(struct i2c_dev_desc * dev)549 static void adi_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
550 {
551 struct i3c_master_controller *m = i2c_dev_get_master(dev);
552 struct adi_i3c_master *master = to_adi_i3c_master(m);
553 struct adi_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
554
555 writel(REG_DEV_CHAR_ADDR(dev->addr) |
556 REG_DEV_CHAR_IS_I2C | REG_DEV_CHAR_WEN,
557 master->regs + REG_DEV_CHAR);
558
559 i2c_dev_set_master_data(dev, NULL);
560 master->free_rr_slots |= BIT(data->id);
561 kfree(data);
562 }
563
adi_i3c_master_bus_cleanup(struct i3c_master_controller * m)564 static void adi_i3c_master_bus_cleanup(struct i3c_master_controller *m)
565 {
566 struct adi_i3c_master *master = to_adi_i3c_master(m);
567
568 adi_i3c_master_disable(master);
569 }
570
adi_i3c_master_upd_i3c_scl_lim(struct adi_i3c_master * master)571 static void adi_i3c_master_upd_i3c_scl_lim(struct adi_i3c_master *master)
572 {
573 struct i3c_master_controller *m = &master->base;
574 struct i3c_bus *bus = i3c_master_get_bus(m);
575 u8 i3c_scl_lim = 0;
576 struct i3c_dev_desc *dev;
577 u8 pp_sg;
578
579 i3c_bus_for_each_i3cdev(bus, dev) {
580 u8 max_fscl;
581
582 max_fscl = max(I3C_CCC_MAX_SDR_FSCL(dev->info.max_read_ds),
583 I3C_CCC_MAX_SDR_FSCL(dev->info.max_write_ds));
584
585 switch (max_fscl) {
586 case I3C_SDR1_FSCL_8MHZ:
587 max_fscl = PP_SG_6MHZ;
588 break;
589 case I3C_SDR2_FSCL_6MHZ:
590 max_fscl = PP_SG_3MHZ;
591 break;
592 case I3C_SDR3_FSCL_4MHZ:
593 max_fscl = PP_SG_3MHZ;
594 break;
595 case I3C_SDR4_FSCL_2MHZ:
596 max_fscl = PP_SG_1MHZ;
597 break;
598 case I3C_SDR0_FSCL_MAX:
599 default:
600 max_fscl = PP_SG_12MHZ;
601 break;
602 }
603
604 if (max_fscl &&
605 (i3c_scl_lim > max_fscl || !i3c_scl_lim))
606 i3c_scl_lim = max_fscl;
607 }
608
609 if (!i3c_scl_lim)
610 return;
611
612 master->i3c_scl_lim = i3c_scl_lim - 1;
613
614 pp_sg = readl(master->regs + REG_OPS) & ~REG_OPS_PP_SG_MASK;
615 pp_sg |= REG_OPS_SET_SG(master->i3c_scl_lim);
616
617 writel(pp_sg, master->regs + REG_OPS);
618 }
619
adi_i3c_master_get_features(struct adi_i3c_master * master,unsigned int slot,struct i3c_device_info * info)620 static void adi_i3c_master_get_features(struct adi_i3c_master *master,
621 unsigned int slot,
622 struct i3c_device_info *info)
623 {
624 u32 buf;
625
626 /* Dynamic address and PID are for identification only */
627 memset(info, 0, sizeof(*info));
628 buf = readl(master->regs + REG_DCR_BCR_DA);
629 info->dyn_addr = REG_DCR_BCR_DA_GET_DA(buf);
630 info->dcr = REG_DCR_BCR_DA_GET_DCR(buf);
631 info->bcr = REG_DCR_BCR_DA_GET_BCR(buf);
632 info->pid = readl(master->regs + REG_PID_L);
633 info->pid |= (u64)readl(master->regs + REG_PID_H) << 32;
634 }
635
adi_i3c_master_do_daa(struct i3c_master_controller * m)636 static int adi_i3c_master_do_daa(struct i3c_master_controller *m)
637 {
638 struct adi_i3c_master *master = to_adi_i3c_master(m);
639 int ret, addr = 0;
640 u32 irq_mask;
641
642 for (u8 i = 0; i < ADI_MAX_DEVS; i++) {
643 addr = i3c_master_get_free_addr(m, addr);
644 if (addr < 0)
645 return addr;
646 master->daa.addrs[i] = addr;
647 }
648
649 irq_mask = readl(master->regs + REG_IRQ_MASK);
650 writel(irq_mask | REG_IRQ_PENDING_DAA,
651 master->regs + REG_IRQ_MASK);
652
653 master->daa.index = 0;
654 ret = i3c_master_entdaa_locked(&master->base);
655
656 writel(irq_mask, master->regs + REG_IRQ_MASK);
657
658 if (ret)
659 return ret;
660
661 /* Add I3C devices discovered */
662 for (u8 i = 0; i < master->daa.index; i++)
663 i3c_master_add_i3c_dev_locked(m, master->daa.addrs[i]);
664 /* Sync retrieved devs info with the IP */
665 adi_i3c_master_sync_dev_char(m);
666
667 i3c_master_defslvs_locked(&master->base);
668
669 adi_i3c_master_upd_i3c_scl_lim(master);
670
671 return 0;
672 }
673
adi_i3c_master_bus_init(struct i3c_master_controller * m)674 static int adi_i3c_master_bus_init(struct i3c_master_controller *m)
675 {
676 struct adi_i3c_master *master = to_adi_i3c_master(m);
677 struct i3c_device_info info = { };
678 int ret;
679
680 ret = i3c_master_get_free_addr(m, 0);
681 if (ret < 0)
682 return ret;
683
684 adi_i3c_master_get_features(master, 0, &info);
685 ret = i3c_master_set_info(&master->base, &info);
686 if (ret)
687 return ret;
688
689 writel(REG_IBI_CONFIG_LISTEN,
690 master->regs + REG_IBI_CONFIG);
691
692 return 0;
693 }
694
adi_i3c_master_handle_ibi(struct adi_i3c_master * master,u32 raw)695 static void adi_i3c_master_handle_ibi(struct adi_i3c_master *master,
696 u32 raw)
697 {
698 struct adi_i3c_i2c_dev_data *data;
699 struct i3c_ibi_slot *slot;
700 struct i3c_dev_desc *dev;
701 u8 da, id, mdb, len;
702 u8 *buf;
703
704 da = FIELD_GET(GENMASK(23, 17), raw);
705 mdb = FIELD_GET(GENMASK(15, 8), raw);
706 for (id = 0; id < master->ibi.num_slots; id++) {
707 if (master->ibi.slots[id] &&
708 master->ibi.slots[id]->info.dyn_addr == da)
709 break;
710 }
711
712 if (id == master->ibi.num_slots)
713 return;
714
715 dev = master->ibi.slots[id];
716 len = ADI_HAS_MDB_FROM_BCR(dev->info.bcr);
717 data = i3c_dev_get_master_data(dev);
718
719 guard(spinlock)(&master->ibi.lock);
720 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
721 if (!slot)
722 return;
723
724 slot->len = len;
725 buf = slot->data;
726 buf[0] = mdb;
727 i3c_master_queue_ibi(dev, slot);
728 }
729
adi_i3c_master_demux_ibis(struct adi_i3c_master * master)730 static void adi_i3c_master_demux_ibis(struct adi_i3c_master *master)
731 {
732 while (!(readl(master->regs + REG_FIFO_STATUS) & REG_FIFO_STATUS_IBI_EMPTY)) {
733 u32 raw = readl(master->regs + REG_IBI_FIFO);
734
735 adi_i3c_master_handle_ibi(master, raw);
736 }
737 }
738
adi_i3c_master_handle_da_req(struct adi_i3c_master * master)739 static void adi_i3c_master_handle_da_req(struct adi_i3c_master *master)
740 {
741 u8 payload0[8];
742 u32 addr;
743
744 adi_i3c_master_rd_from_rx_fifo(master, payload0, 6);
745 addr = master->daa.addrs[master->daa.index++];
746 addr = (addr << 1) | (parity8(addr) ? 0 : 1);
747
748 writel(addr, master->regs + REG_SDO_FIFO);
749 }
750
adi_i3c_master_irq(int irq,void * data)751 static irqreturn_t adi_i3c_master_irq(int irq, void *data)
752 {
753 struct adi_i3c_master *master = data;
754 u32 pending;
755
756 pending = readl(master->regs + REG_IRQ_PENDING);
757 writel(pending, master->regs + REG_IRQ_PENDING);
758 if (pending & REG_IRQ_PENDING_CMDR) {
759 scoped_guard(spinlock_irqsave, &master->xferqueue.lock) {
760 adi_i3c_master_end_xfer_locked(master, pending);
761 }
762 }
763 if (pending & REG_IRQ_PENDING_IBI)
764 adi_i3c_master_demux_ibis(master);
765 if (pending & REG_IRQ_PENDING_DAA)
766 adi_i3c_master_handle_da_req(master);
767
768 return IRQ_HANDLED;
769 }
770
adi_i3c_master_i2c_xfers(struct i2c_dev_desc * dev,struct i2c_msg * xfers,int nxfers)771 static int adi_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
772 struct i2c_msg *xfers,
773 int nxfers)
774 {
775 struct i3c_master_controller *m = i2c_dev_get_master(dev);
776 struct adi_i3c_master *master = to_adi_i3c_master(m);
777 int i;
778
779 if (!nxfers)
780 return 0;
781 for (i = 0; i < nxfers; i++) {
782 if (xfers[i].flags & I2C_M_TEN)
783 return -EOPNOTSUPP;
784 }
785
786 struct adi_i3c_xfer *xfer __free(kfree) = adi_i3c_master_alloc_xfer(master, nxfers);
787 if (!xfer)
788 return -ENOMEM;
789
790 for (i = 0; i < nxfers; i++) {
791 struct adi_i3c_cmd *ccmd = &xfer->cmds[i];
792
793 ccmd->cmd0 = REG_CMD_FIFO_0_DEV_ADDR(xfers[i].addr);
794
795 if (xfers[i].flags & I2C_M_RD) {
796 ccmd->cmd0 |= REG_CMD_FIFO_0_RNW;
797 ccmd->rx_buf = xfers[i].buf;
798 ccmd->rx_len = xfers[i].len;
799 } else {
800 ccmd->tx_buf = xfers[i].buf;
801 ccmd->tx_len = xfers[i].len;
802 }
803
804 ccmd->cmd0 |= REG_CMD_FIFO_0_LEN(xfers[i].len);
805 }
806
807 adi_i3c_master_queue_xfer(master, xfer);
808 if (!wait_for_completion_timeout(&xfer->comp,
809 m->i2c.timeout))
810 adi_i3c_master_unqueue_xfer(master, xfer);
811
812 return xfer->ret;
813 }
814
adi_i3c_master_disable_ibi(struct i3c_dev_desc * dev)815 static int adi_i3c_master_disable_ibi(struct i3c_dev_desc *dev)
816 {
817 struct i3c_master_controller *m = i3c_dev_get_master(dev);
818 struct adi_i3c_master *master = to_adi_i3c_master(m);
819 struct i3c_dev_desc *i3cdev;
820 u32 enabled = 0;
821 int ret;
822
823 ret = i3c_master_disec_locked(m, dev->info.dyn_addr,
824 I3C_CCC_EVENT_SIR);
825
826 i3c_bus_for_each_i3cdev(&m->bus, i3cdev) {
827 if (dev != i3cdev && i3cdev->ibi)
828 enabled |= i3cdev->ibi->enabled;
829 }
830 if (!enabled) {
831 writel(REG_IBI_CONFIG_LISTEN,
832 master->regs + REG_IBI_CONFIG);
833 writel(readl(master->regs + REG_IRQ_MASK) & ~REG_IRQ_PENDING_IBI,
834 master->regs + REG_IRQ_MASK);
835 }
836
837 return ret;
838 }
839
adi_i3c_master_enable_ibi(struct i3c_dev_desc * dev)840 static int adi_i3c_master_enable_ibi(struct i3c_dev_desc *dev)
841 {
842 struct i3c_master_controller *m = i3c_dev_get_master(dev);
843 struct adi_i3c_master *master = to_adi_i3c_master(m);
844
845 writel(REG_IBI_CONFIG_LISTEN | REG_IBI_CONFIG_ENABLE,
846 master->regs + REG_IBI_CONFIG);
847
848 writel(readl(master->regs + REG_IRQ_MASK) | REG_IRQ_PENDING_IBI,
849 master->regs + REG_IRQ_MASK);
850
851 return i3c_master_enec_locked(m, dev->info.dyn_addr,
852 I3C_CCC_EVENT_SIR);
853 }
854
adi_i3c_master_request_ibi(struct i3c_dev_desc * dev,const struct i3c_ibi_setup * req)855 static int adi_i3c_master_request_ibi(struct i3c_dev_desc *dev,
856 const struct i3c_ibi_setup *req)
857 {
858 struct i3c_master_controller *m = i3c_dev_get_master(dev);
859 struct adi_i3c_master *master = to_adi_i3c_master(m);
860 struct adi_i3c_i2c_dev_data *data;
861 unsigned int i;
862
863 data = i3c_dev_get_master_data(dev);
864 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req);
865 if (IS_ERR(data->ibi_pool))
866 return PTR_ERR(data->ibi_pool);
867
868 scoped_guard(spinlock_irqsave, &master->ibi.lock) {
869 for (i = 0; i < master->ibi.num_slots; i++) {
870 if (!master->ibi.slots[i]) {
871 data->ibi = i;
872 master->ibi.slots[i] = dev;
873 break;
874 }
875 }
876 }
877
878 if (i < master->ibi.num_slots)
879 return 0;
880
881 i3c_generic_ibi_free_pool(data->ibi_pool);
882 data->ibi_pool = NULL;
883
884 return -ENOSPC;
885 }
886
adi_i3c_master_free_ibi(struct i3c_dev_desc * dev)887 static void adi_i3c_master_free_ibi(struct i3c_dev_desc *dev)
888 {
889 struct i3c_master_controller *m = i3c_dev_get_master(dev);
890 struct adi_i3c_master *master = to_adi_i3c_master(m);
891 struct adi_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
892
893 scoped_guard(spinlock_irqsave, &master->ibi.lock) {
894 master->ibi.slots[data->ibi] = NULL;
895 }
896
897 i3c_generic_ibi_free_pool(data->ibi_pool);
898 }
899
adi_i3c_master_recycle_ibi_slot(struct i3c_dev_desc * dev,struct i3c_ibi_slot * slot)900 static void adi_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev,
901 struct i3c_ibi_slot *slot)
902 {
903 struct adi_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
904
905 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot);
906 }
907
908 static const struct i3c_master_controller_ops adi_i3c_master_ops = {
909 .bus_init = adi_i3c_master_bus_init,
910 .bus_cleanup = adi_i3c_master_bus_cleanup,
911 .attach_i3c_dev = adi_i3c_master_attach_i3c_dev,
912 .reattach_i3c_dev = adi_i3c_master_reattach_i3c_dev,
913 .detach_i3c_dev = adi_i3c_master_detach_i3c_dev,
914 .attach_i2c_dev = adi_i3c_master_attach_i2c_dev,
915 .detach_i2c_dev = adi_i3c_master_detach_i2c_dev,
916 .do_daa = adi_i3c_master_do_daa,
917 .supports_ccc_cmd = adi_i3c_master_supports_ccc_cmd,
918 .send_ccc_cmd = adi_i3c_master_send_ccc_cmd,
919 .i3c_xfers = adi_i3c_master_i3c_xfers,
920 .i2c_xfers = adi_i3c_master_i2c_xfers,
921 .request_ibi = adi_i3c_master_request_ibi,
922 .enable_ibi = adi_i3c_master_enable_ibi,
923 .disable_ibi = adi_i3c_master_disable_ibi,
924 .free_ibi = adi_i3c_master_free_ibi,
925 .recycle_ibi_slot = adi_i3c_master_recycle_ibi_slot,
926 };
927
928 static const struct of_device_id adi_i3c_master_of_match[] = {
929 { .compatible = "adi,i3c-master-v1" },
930 {}
931 };
932
adi_i3c_master_probe(struct platform_device * pdev)933 static int adi_i3c_master_probe(struct platform_device *pdev)
934 {
935 struct adi_i3c_master *master;
936 struct clk_bulk_data *clk;
937 unsigned int version;
938 int ret, irq;
939
940 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
941 if (!master)
942 return -ENOMEM;
943
944 master->regs = devm_platform_ioremap_resource(pdev, 0);
945 if (IS_ERR(master->regs))
946 return PTR_ERR(master->regs);
947
948 ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clk);
949 if (ret < 0)
950 return dev_err_probe(&pdev->dev, ret,
951 "Failed to get clocks\n");
952
953 irq = platform_get_irq(pdev, 0);
954 if (irq < 0)
955 return irq;
956
957 version = readl(master->regs + ADI_AXI_REG_VERSION);
958 if (ADI_AXI_PCORE_VER_MAJOR(version) != 1)
959 dev_err_probe(&pdev->dev, -ENODEV, "Unsupported peripheral version %u.%u.%u\n",
960 ADI_AXI_PCORE_VER_MAJOR(version),
961 ADI_AXI_PCORE_VER_MINOR(version),
962 ADI_AXI_PCORE_VER_PATCH(version));
963
964 writel(0x00, master->regs + REG_ENABLE);
965 writel(0x00, master->regs + REG_IRQ_MASK);
966
967 ret = devm_request_irq(&pdev->dev, irq, adi_i3c_master_irq, 0,
968 dev_name(&pdev->dev), master);
969 if (ret)
970 return ret;
971
972 platform_set_drvdata(pdev, master);
973
974 master->free_rr_slots = GENMASK(ADI_MAX_DEVS, 1);
975
976 writel(REG_IRQ_PENDING_CMDR, master->regs + REG_IRQ_MASK);
977
978 spin_lock_init(&master->ibi.lock);
979 master->ibi.num_slots = 15;
980 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots,
981 sizeof(*master->ibi.slots),
982 GFP_KERNEL);
983 if (!master->ibi.slots)
984 return -ENOMEM;
985
986 spin_lock_init(&master->xferqueue.lock);
987 INIT_LIST_HEAD(&master->xferqueue.list);
988
989 return i3c_master_register(&master->base, &pdev->dev,
990 &adi_i3c_master_ops, false);
991 }
992
adi_i3c_master_remove(struct platform_device * pdev)993 static void adi_i3c_master_remove(struct platform_device *pdev)
994 {
995 struct adi_i3c_master *master = platform_get_drvdata(pdev);
996
997 writel(0xff, master->regs + REG_IRQ_PENDING);
998 writel(0x00, master->regs + REG_IRQ_MASK);
999 writel(0x01, master->regs + REG_ENABLE);
1000
1001 i3c_master_unregister(&master->base);
1002 }
1003
1004 static struct platform_driver adi_i3c_master = {
1005 .probe = adi_i3c_master_probe,
1006 .remove = adi_i3c_master_remove,
1007 .driver = {
1008 .name = "adi-i3c-master",
1009 .of_match_table = adi_i3c_master_of_match,
1010 },
1011 };
1012 module_platform_driver(adi_i3c_master);
1013
1014 MODULE_AUTHOR("Jorge Marques <jorge.marques@analog.com>");
1015 MODULE_DESCRIPTION("Analog Devices I3C master driver");
1016 MODULE_LICENSE("GPL");
1017