1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2026 Analog Devices, Inc.
4 * Author: Marcelo Schmitt <marcelo.schmitt@analog.com>
5 */
6
7 #include <linux/array_size.h>
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/crc8.h>
12 #include <linux/delay.h>
13 #include <linux/dev_printk.h>
14 #include <linux/err.h>
15 #include <linux/export.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/iio/iio.h>
18 #include <linux/iio/types.h>
19 #include <linux/module.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/reset.h>
24 #include <linux/spi/spi.h>
25 #include <linux/time.h>
26 #include <linux/types.h>
27 #include <linux/unaligned.h>
28 #include <linux/units.h>
29
30 #define AD4134_RESET_TIME_US (10 * USEC_PER_SEC)
31
32 #define AD4134_REG_READ_MASK BIT(7)
33 #define AD4134_SPI_MAX_XFER_LEN 3
34
35 #define AD4134_EXT_CLOCK_MHZ (48 * HZ_PER_MHZ)
36
37 #define AD4134_NUM_CHANNELS 4
38 #define AD4134_CHAN_PRECISION_BITS 24
39
40 #define AD4134_IFACE_CONFIG_A_REG 0x00
41 #define AD4134_IFACE_CONFIG_B_REG 0x01
42 #define AD4134_IFACE_CONFIG_B_SINGLE_INSTR BIT(7)
43
44 #define AD4134_DEVICE_CONFIG_REG 0x02
45 #define AD4134_DEVICE_CONFIG_POWER_MODE_MASK BIT(0)
46 #define AD4134_POWER_MODE_HIGH_PERF 0x1
47
48 #define AD4134_SILICON_REV_REG 0x07
49 #define AD4134_SCRATCH_PAD_REG 0x0A
50 #define AD4134_STREAM_MODE_REG 0x0E
51 #define AD4134_SDO_PIN_SRC_SEL_REG 0x10
52 #define AD4134_SDO_PIN_SRC_SEL_SDO_SEL_MASK BIT(2)
53
54 #define AD4134_DATA_PACKET_CONFIG_REG 0x11
55 #define AD4134_DATA_PACKET_CONFIG_FRAME_MASK GENMASK(5, 4)
56 #define AD4134_DATA_PACKET_24BIT_FRAME 0x2
57
58 #define AD4134_DIG_IF_CFG_REG 0x12
59 #define AD4134_DIF_IF_CFG_FORMAT_MASK GENMASK(1, 0)
60 #define AD4134_DATA_FORMAT_SINGLE_CH_MODE 0x0
61
62 #define AD4134_PW_DOWN_CTRL_REG 0x13
63 #define AD4134_DEVICE_STATUS_REG 0x15
64 #define AD4134_ODR_VAL_INT_LSB_REG 0x16
65 #define AD4134_CH3_OFFSET_MSB_REG 0x3E
66 #define AD4134_AIN_OR_ERROR_REG 0x48
67
68 /*
69 * AD4134 register map ends at address 0x48 and there is no register for
70 * retrieving ADC sample data. Though, to make use of Linux regmap API both
71 * for register access and sample read, we define one virtual register for each
72 * ADC channel. AD4134_CH_VREG(x) maps a channel number to it's virtual register
73 * address while AD4134_VREG_CH(x) tells which channel given the address.
74 */
75 #define AD4134_CH_VREG(x) ((x) + 0x50)
76 #define AD4134_VREG_CH(x) ((x) - 0x50)
77
78 #define AD4134_SPI_CRC_POLYNOM 0x07
79 #define AD4134_SPI_CRC_INIT_VALUE 0xA5
80 static unsigned char ad4134_spi_crc_table[CRC8_TABLE_SIZE];
81
82 #define AD4134_CHANNEL(_index) { \
83 .type = IIO_VOLTAGE, \
84 .indexed = 1, \
85 .channel = (_index), \
86 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
87 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
88 }
89
90 static const struct iio_chan_spec ad4134_chan_set[] = {
91 AD4134_CHANNEL(0),
92 AD4134_CHANNEL(1),
93 AD4134_CHANNEL(2),
94 AD4134_CHANNEL(3),
95 };
96
97 struct ad4134_state {
98 struct spi_device *spi;
99 struct regmap *regmap;
100 unsigned long sys_clk_hz;
101 struct gpio_desc *odr_gpio;
102 int refin_mv;
103 /*
104 * DMA (thus cache coherency maintenance) requires the transfer buffers
105 * to live in their own cache lines.
106 */
107 u8 rx_buf[AD4134_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN);
108 u8 tx_buf[AD4134_SPI_MAX_XFER_LEN];
109 };
110
111 static const struct regmap_range ad4134_regmap_rd_range[] = {
112 regmap_reg_range(AD4134_IFACE_CONFIG_A_REG, AD4134_SILICON_REV_REG),
113 regmap_reg_range(AD4134_SCRATCH_PAD_REG, AD4134_PW_DOWN_CTRL_REG),
114 regmap_reg_range(AD4134_DEVICE_STATUS_REG, AD4134_AIN_OR_ERROR_REG),
115 regmap_reg_range(AD4134_CH_VREG(0), AD4134_CH_VREG(AD4134_NUM_CHANNELS)),
116 };
117
118 static const struct regmap_range ad4134_regmap_wr_range[] = {
119 regmap_reg_range(AD4134_IFACE_CONFIG_A_REG, AD4134_DEVICE_CONFIG_REG),
120 regmap_reg_range(AD4134_SCRATCH_PAD_REG, AD4134_SCRATCH_PAD_REG),
121 regmap_reg_range(AD4134_STREAM_MODE_REG, AD4134_PW_DOWN_CTRL_REG),
122 regmap_reg_range(AD4134_ODR_VAL_INT_LSB_REG, AD4134_CH3_OFFSET_MSB_REG),
123 };
124
125 static const struct regmap_access_table ad4134_regmap_rd_table = {
126 .yes_ranges = ad4134_regmap_rd_range,
127 .n_yes_ranges = ARRAY_SIZE(ad4134_regmap_rd_range),
128 };
129
130 static const struct regmap_access_table ad4134_regmap_wr_table = {
131 .yes_ranges = ad4134_regmap_wr_range,
132 .n_yes_ranges = ARRAY_SIZE(ad4134_regmap_wr_range),
133 };
134
ad4134_calc_spi_crc(u8 inst,u8 data)135 static int ad4134_calc_spi_crc(u8 inst, u8 data)
136 {
137 u8 buf[] = { inst, data };
138
139 return crc8(ad4134_spi_crc_table, buf, ARRAY_SIZE(buf),
140 AD4134_SPI_CRC_INIT_VALUE);
141 }
142
ad4134_prepare_spi_tx_buf(u8 inst,u8 data,u8 * buf)143 static void ad4134_prepare_spi_tx_buf(u8 inst, u8 data, u8 *buf)
144 {
145 buf[0] = inst;
146 buf[1] = data;
147 buf[2] = ad4134_calc_spi_crc(inst, data);
148 }
149
ad4134_reg_write(void * context,unsigned int reg,unsigned int val)150 static int ad4134_reg_write(void *context, unsigned int reg, unsigned int val)
151 {
152 struct ad4134_state *st = context;
153 struct spi_transfer xfer = {
154 .tx_buf = st->tx_buf,
155 .rx_buf = st->rx_buf,
156 .len = AD4134_SPI_MAX_XFER_LEN,
157 };
158 int ret;
159
160 ad4134_prepare_spi_tx_buf(reg, val, st->tx_buf);
161
162 ret = spi_sync_transfer(st->spi, &xfer, 1);
163 if (ret)
164 return ret;
165
166 if (st->rx_buf[2] != st->tx_buf[2])
167 dev_dbg(&st->spi->dev, "reg write CRC check failed\n");
168
169 return 0;
170 }
171
ad4134_data_read(struct ad4134_state * st,unsigned int reg,unsigned int * val)172 static int ad4134_data_read(struct ad4134_state *st, unsigned int reg,
173 unsigned int *val)
174 {
175 unsigned int i;
176 int ret;
177
178 /*
179 * To be able to read data from all 4 channels through a single line, we
180 * set DOUTx output format to 0 in the digital interface config register
181 * (0x12). With that, data from all four channels is serialized and
182 * output on DOUT0. During the probe, we also set SDO_PIN_SRC_SEL in
183 * DEVICE_CONFIG_1 register to duplicate DOUT0 on the SDO pin. Combined,
184 * those configurations enable ADC data read through a conventional SPI
185 * interface. Now we read data from all channels but keep only the bits
186 * from the requested one.
187 */
188 for (i = 0; i < ARRAY_SIZE(ad4134_chan_set); i++) {
189 ret = spi_write_then_read(st->spi, NULL, 0, st->rx_buf,
190 BITS_TO_BYTES(AD4134_CHAN_PRECISION_BITS));
191 if (ret)
192 return ret;
193
194 /*
195 * AD4134 has a built-in feature that flags when data transfers
196 * don't run enough clock cycles to read the entire data frame.
197 * Clock out data from all channels to avoid that.
198 */
199 if (i == AD4134_VREG_CH(reg))
200 *val = get_unaligned_be24(st->rx_buf);
201 }
202
203 return 0;
204 }
205
ad4134_register_read(struct ad4134_state * st,unsigned int reg,unsigned int * val)206 static int ad4134_register_read(struct ad4134_state *st, unsigned int reg,
207 unsigned int *val)
208 {
209 struct spi_transfer xfer = {
210 .tx_buf = st->tx_buf,
211 .rx_buf = st->rx_buf,
212 .len = AD4134_SPI_MAX_XFER_LEN,
213 };
214 unsigned int inst;
215 int ret;
216
217 inst = AD4134_REG_READ_MASK | reg;
218 ad4134_prepare_spi_tx_buf(inst, 0, st->tx_buf);
219
220 ret = spi_sync_transfer(st->spi, &xfer, 1);
221 if (ret)
222 return ret;
223
224 *val = st->rx_buf[1];
225
226 /* Check CRC */
227 if (st->rx_buf[2] != st->tx_buf[2])
228 dev_dbg(&st->spi->dev, "reg read CRC check failed\n");
229
230 return 0;
231 }
232
ad4134_reg_read(void * context,unsigned int reg,unsigned int * val)233 static int ad4134_reg_read(void *context, unsigned int reg, unsigned int *val)
234 {
235 struct ad4134_state *st = context;
236
237 if (reg >= AD4134_CH_VREG(0))
238 return ad4134_data_read(st, reg, val);
239
240 return ad4134_register_read(st, reg, val);
241 }
242
243 static const struct regmap_config ad4134_regmap_config = {
244 .reg_read = ad4134_reg_read,
245 .reg_write = ad4134_reg_write,
246 .rd_table = &ad4134_regmap_rd_table,
247 .wr_table = &ad4134_regmap_wr_table,
248 .max_register = AD4134_CH_VREG(ARRAY_SIZE(ad4134_chan_set)),
249 };
250
ad4134_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)251 static int ad4134_read_raw(struct iio_dev *indio_dev,
252 struct iio_chan_spec const *chan,
253 int *val, int *val2, long info)
254 {
255 struct ad4134_state *st = iio_priv(indio_dev);
256 int ret;
257
258 switch (info) {
259 case IIO_CHAN_INFO_RAW:
260 gpiod_set_value_cansleep(st->odr_gpio, 1);
261 /*
262 * For slave mode gated DCLK (data sheet page 11), the minimum
263 * ODR high time is 3 * tDIGCLK. The internal digital clock
264 * period is tDIGCLK = 1/fDIGCLK = 2/fSYSCLK.
265 * The System clock frequency (fSYSCLK) is typically 48 MHz.
266 * Thus, ODR high time = 3 * (2 / (48 * HZ_PER_MHZ))
267 * ODR high time = 0.000000125 s = 125 ns
268 * 1 micro second should be more than enough. Not worth it
269 * tweaking for shorter dealy since this is not a fast data path.
270 */
271 fsleep(1);
272 gpiod_set_value_cansleep(st->odr_gpio, 0);
273 ret = regmap_read(st->regmap, AD4134_CH_VREG(chan->channel), val);
274 if (ret)
275 return ret;
276
277 return IIO_VAL_INT;
278 case IIO_CHAN_INFO_SCALE:
279 *val = st->refin_mv;
280 *val2 = AD4134_CHAN_PRECISION_BITS - 1;
281
282 return IIO_VAL_FRACTIONAL_LOG2;
283 default:
284 return -EINVAL;
285 }
286 }
287
ad4134_debugfs_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)288 static int ad4134_debugfs_reg_access(struct iio_dev *indio_dev,
289 unsigned int reg, unsigned int writeval,
290 unsigned int *readval)
291 {
292 struct ad4134_state *st = iio_priv(indio_dev);
293
294 if (readval)
295 return regmap_read(st->regmap, reg, readval);
296
297 return regmap_write(st->regmap, reg, writeval);
298 }
299
ad4134_min_io_mode_setup(struct ad4134_state * st)300 static int ad4134_min_io_mode_setup(struct ad4134_state *st)
301 {
302 struct device *dev = &st->spi->dev;
303 int ret;
304
305 st->odr_gpio = devm_gpiod_get(dev, "odr", GPIOD_OUT_LOW);
306 if (IS_ERR(st->odr_gpio))
307 return dev_err_probe(dev, PTR_ERR(st->odr_gpio),
308 "failed to get ODR GPIO\n");
309
310 ret = regmap_update_bits(st->regmap, AD4134_DIG_IF_CFG_REG,
311 AD4134_DIF_IF_CFG_FORMAT_MASK,
312 FIELD_PREP(AD4134_DIF_IF_CFG_FORMAT_MASK,
313 AD4134_DATA_FORMAT_SINGLE_CH_MODE));
314 if (ret)
315 return dev_err_probe(dev, ret,
316 "failed to set single channel mode\n");
317
318 ret = regmap_set_bits(st->regmap, AD4134_SDO_PIN_SRC_SEL_REG,
319 AD4134_SDO_PIN_SRC_SEL_SDO_SEL_MASK);
320 if (ret)
321 return dev_err_probe(dev, ret,
322 "failed to set SDO source selection\n");
323
324 return regmap_set_bits(st->regmap, AD4134_IFACE_CONFIG_B_REG,
325 AD4134_IFACE_CONFIG_B_SINGLE_INSTR);
326 }
327
328 static const struct iio_info ad4134_info = {
329 .read_raw = ad4134_read_raw,
330 .debugfs_reg_access = ad4134_debugfs_reg_access,
331 };
332
333 static const char * const ad4143_required_regulators[] = {
334 "avdd5", "dvdd5", "iovdd",
335 };
336
337 static const char * const ad4143_optional_regulators[] = {
338 "avdd1v8", "dvdd1v8", "clkvdd",
339 };
340
ad4134_regulator_setup(struct ad4134_state * st)341 static int ad4134_regulator_setup(struct ad4134_state *st)
342 {
343 struct device *dev = &st->spi->dev;
344 int ret;
345
346 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad4143_required_regulators),
347 ad4143_required_regulators);
348 if (ret)
349 return dev_err_probe(dev, ret, "failed to enable power supplies\n");
350
351 /* Required regulator that we need to read the voltage */
352 ret = devm_regulator_get_enable_read_voltage(dev, "refin");
353 if (ret < 0)
354 return dev_err_probe(dev, ret, "failed to get REFIN voltage.\n");
355
356 st->refin_mv = ret / (MICRO / MILLI);
357
358 ret = devm_regulator_get_enable_optional(dev, "ldoin");
359 if (ret < 0 && ret != -ENODEV)
360 return dev_err_probe(dev, ret, "failed to enable ldoin supply\n");
361
362 /* If ldoin was provided, then use the use the internal LDO regulators */
363 if (ret == 0)
364 return 0;
365
366 /*
367 * If ldoin is not provided, then avdd1v8, dvdd1v8, and clkvdd are
368 * required.
369 */
370 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad4143_optional_regulators),
371 ad4143_optional_regulators);
372 if (ret)
373 return dev_err_probe(dev, ret, "failed to enable 1V8 power supplies\n");
374
375 return 0;
376 }
377
ad4134_clock_select(struct ad4134_state * st)378 static int ad4134_clock_select(struct ad4134_state *st)
379 {
380 struct device *dev = &st->spi->dev;
381 struct clk *xtal_clk, *clkin_clk;
382
383 /*
384 * AD4134 requires one external clock source and only one external clock
385 * source can be provided at a time. Try to get a crystal provided clock.
386 * If that fails, try to get a CMOS clock.
387 */
388 xtal_clk = devm_clk_get_optional_enabled(dev, "xtal");
389 if (!xtal_clk)
390 xtal_clk = devm_clk_get_optional_enabled(dev, "xtal");
391 if (IS_ERR(xtal_clk))
392 return dev_err_probe(dev, PTR_ERR(xtal_clk),
393 "failed to get xtal\n");
394
395 clkin_clk = devm_clk_get_optional_enabled(dev, "clkin");
396 if (!clkin_clk)
397 clkin_clk = devm_clk_get_optional_enabled(dev, "clkin");
398 if (IS_ERR(clkin_clk))
399 return dev_err_probe(dev, PTR_ERR(clkin_clk),
400 "failed to get clkin\n");
401
402 st->sys_clk_hz = clk_get_rate(xtal_clk) | clk_get_rate(clkin_clk);
403 if (st->sys_clk_hz != AD4134_EXT_CLOCK_MHZ)
404 dev_warn(dev, "invalid external clock frequency %lu\n",
405 st->sys_clk_hz);
406
407 return 0;
408 }
409
ad4134_probe(struct spi_device * spi)410 static int ad4134_probe(struct spi_device *spi)
411 {
412 struct device *dev = &spi->dev;
413 struct reset_control *rst;
414 struct iio_dev *indio_dev;
415 struct ad4134_state *st;
416 int ret;
417
418 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
419 if (!indio_dev)
420 return -ENOMEM;
421
422 st = iio_priv(indio_dev);
423 st->spi = spi;
424
425 indio_dev->name = "ad4134";
426 indio_dev->channels = ad4134_chan_set;
427 indio_dev->num_channels = ARRAY_SIZE(ad4134_chan_set);
428 indio_dev->modes = INDIO_DIRECT_MODE;
429 indio_dev->info = &ad4134_info;
430
431 ret = ad4134_regulator_setup(st);
432 if (ret)
433 return ret;
434
435 ret = ad4134_clock_select(st);
436 if (ret)
437 return ret;
438
439 rst = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL);
440 if (IS_ERR(rst))
441 return dev_err_probe(dev, PTR_ERR(rst),
442 "failed to get and deassert reset\n");
443
444 crc8_populate_msb(ad4134_spi_crc_table, AD4134_SPI_CRC_POLYNOM);
445
446 st->regmap = devm_regmap_init(dev, NULL, st, &ad4134_regmap_config);
447 if (IS_ERR(st->regmap))
448 return dev_err_probe(dev, PTR_ERR(st->regmap),
449 "failed to initialize regmap");
450
451 ret = ad4134_min_io_mode_setup(st);
452 if (ret)
453 return dev_err_probe(dev, ret,
454 "failed to setup minimum I/O mode\n");
455
456 /* Bump precision to 24-bit */
457 ret = regmap_update_bits(st->regmap, AD4134_DATA_PACKET_CONFIG_REG,
458 AD4134_DATA_PACKET_CONFIG_FRAME_MASK,
459 FIELD_PREP(AD4134_DATA_PACKET_CONFIG_FRAME_MASK,
460 AD4134_DATA_PACKET_24BIT_FRAME));
461 if (ret)
462 return ret;
463
464 /* Set high performance power mode */
465 ret = regmap_update_bits(st->regmap, AD4134_DEVICE_CONFIG_REG,
466 AD4134_DEVICE_CONFIG_POWER_MODE_MASK,
467 FIELD_PREP(AD4134_DEVICE_CONFIG_POWER_MODE_MASK,
468 AD4134_POWER_MODE_HIGH_PERF));
469 if (ret)
470 return ret;
471
472 return devm_iio_device_register(dev, indio_dev);
473 }
474
475 static const struct spi_device_id ad4134_id[] = {
476 { "ad4134" },
477 { }
478 };
479 MODULE_DEVICE_TABLE(spi, ad4134_id);
480
481 static const struct of_device_id ad4134_of_match[] = {
482 { .compatible = "adi,ad4134" },
483 { }
484 };
485 MODULE_DEVICE_TABLE(of, ad4134_of_match);
486
487 static struct spi_driver ad4134_driver = {
488 .driver = {
489 .name = "ad4134",
490 .of_match_table = ad4134_of_match,
491 },
492 .probe = ad4134_probe,
493 .id_table = ad4134_id,
494 };
495 module_spi_driver(ad4134_driver);
496
497 MODULE_AUTHOR("Marcelo Schmitt <marcelo.schmitt@analog.com>");
498 MODULE_DESCRIPTION("Analog Devices AD4134 SPI driver");
499 MODULE_LICENSE("GPL");
500 MODULE_IMPORT_NS("IIO_AD4134");
501