1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Implementation of the IOMMU SVA API for the ARM SMMUv3
4 */
5
6 #include <linux/mm.h>
7 #include <linux/mmu_context.h>
8 #include <linux/mmu_notifier.h>
9 #include <linux/sched/mm.h>
10 #include <linux/slab.h>
11 #include <kunit/visibility.h>
12
13 #include "arm-smmu-v3.h"
14 #include "../../io-pgtable-arm.h"
15
16 static void __maybe_unused
arm_smmu_update_s1_domain_cd_entry(struct arm_smmu_domain * smmu_domain)17 arm_smmu_update_s1_domain_cd_entry(struct arm_smmu_domain *smmu_domain)
18 {
19 struct arm_smmu_master_domain *master_domain;
20 struct arm_smmu_cd target_cd;
21 unsigned long flags;
22
23 spin_lock_irqsave(&smmu_domain->devices_lock, flags);
24 list_for_each_entry(master_domain, &smmu_domain->devices, devices_elm) {
25 struct arm_smmu_master *master = master_domain->master;
26 struct arm_smmu_cd *cdptr;
27
28 cdptr = arm_smmu_get_cd_ptr(master, master_domain->ssid);
29 if (WARN_ON(!cdptr))
30 continue;
31
32 arm_smmu_make_s1_cd(&target_cd, master, smmu_domain);
33 arm_smmu_write_cd_entry(master, master_domain->ssid, cdptr,
34 &target_cd);
35 }
36 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
37 }
38
page_size_to_cd(void)39 static u64 page_size_to_cd(void)
40 {
41 static_assert(PAGE_SIZE == SZ_4K || PAGE_SIZE == SZ_16K ||
42 PAGE_SIZE == SZ_64K);
43 if (PAGE_SIZE == SZ_64K)
44 return ARM_LPAE_TCR_TG0_64K;
45 if (PAGE_SIZE == SZ_16K)
46 return ARM_LPAE_TCR_TG0_16K;
47 return ARM_LPAE_TCR_TG0_4K;
48 }
49
50 VISIBLE_IF_KUNIT
arm_smmu_make_sva_cd(struct arm_smmu_cd * target,struct arm_smmu_master * master,struct mm_struct * mm,u16 asid)51 void arm_smmu_make_sva_cd(struct arm_smmu_cd *target,
52 struct arm_smmu_master *master, struct mm_struct *mm,
53 u16 asid)
54 {
55 u64 par;
56
57 memset(target, 0, sizeof(*target));
58
59 par = cpuid_feature_extract_unsigned_field(
60 read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1),
61 ID_AA64MMFR0_EL1_PARANGE_SHIFT);
62
63 target->data[0] = cpu_to_le64(
64 CTXDESC_CD_0_TCR_EPD1 |
65 #ifdef __BIG_ENDIAN
66 CTXDESC_CD_0_ENDI |
67 #endif
68 CTXDESC_CD_0_V |
69 FIELD_PREP(CTXDESC_CD_0_TCR_IPS, par) |
70 CTXDESC_CD_0_AA64 |
71 (master->stall_enabled ? CTXDESC_CD_0_S : 0) |
72 CTXDESC_CD_0_R |
73 CTXDESC_CD_0_A |
74 CTXDESC_CD_0_ASET |
75 FIELD_PREP(CTXDESC_CD_0_ASID, asid));
76
77 /*
78 * If no MM is passed then this creates a SVA entry that faults
79 * everything. arm_smmu_write_cd_entry() can hitlessly go between these
80 * two entries types since TTB0 is ignored by HW when EPD0 is set.
81 */
82 if (mm) {
83 target->data[0] |= cpu_to_le64(
84 FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ,
85 64ULL - vabits_actual) |
86 FIELD_PREP(CTXDESC_CD_0_TCR_TG0, page_size_to_cd()) |
87 FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0,
88 ARM_LPAE_TCR_RGN_WBWA) |
89 FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0,
90 ARM_LPAE_TCR_RGN_WBWA) |
91 FIELD_PREP(CTXDESC_CD_0_TCR_SH0, ARM_LPAE_TCR_SH_IS));
92
93 target->data[1] = cpu_to_le64(virt_to_phys(mm->pgd) &
94 CTXDESC_CD_1_TTB0_MASK);
95 } else {
96 target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_EPD0);
97
98 /*
99 * Disable stall and immediately generate an abort if stall
100 * disable is permitted. This speeds up cleanup for an unclean
101 * exit if the device is still doing a lot of DMA.
102 */
103 if (!(master->smmu->features & ARM_SMMU_FEAT_STALL_FORCE))
104 target->data[0] &=
105 cpu_to_le64(~(CTXDESC_CD_0_S | CTXDESC_CD_0_R));
106 }
107
108 /*
109 * MAIR value is pretty much constant and global, so we can just get it
110 * from the current CPU register
111 */
112 target->data[3] = cpu_to_le64(read_sysreg(mair_el1));
113
114 /*
115 * Note that we don't bother with S1PIE on the SMMU, we just rely on
116 * our default encoding scheme matching direct permissions anyway.
117 * SMMU has no notion of S1POE nor GCS, so make sure that is clear if
118 * either is enabled for CPUs, just in case anyone imagines otherwise.
119 */
120 if (system_supports_poe() || system_supports_gcs())
121 dev_warn_once(master->smmu->dev, "SVA devices ignore permission overlays and GCS\n");
122 }
123 EXPORT_SYMBOL_IF_KUNIT(arm_smmu_make_sva_cd);
124
arm_smmu_mm_arch_invalidate_secondary_tlbs(struct mmu_notifier * mn,struct mm_struct * mm,unsigned long start,unsigned long end)125 static void arm_smmu_mm_arch_invalidate_secondary_tlbs(struct mmu_notifier *mn,
126 struct mm_struct *mm,
127 unsigned long start,
128 unsigned long end)
129 {
130 struct arm_smmu_domain *smmu_domain =
131 container_of(mn, struct arm_smmu_domain, mmu_notifier);
132 size_t size;
133
134 /*
135 * The mm_types defines vm_end as the first byte after the end address,
136 * different from IOMMU subsystem using the last address of an address
137 * range. So do a simple translation here by calculating size correctly.
138 */
139 size = end - start;
140
141 arm_smmu_domain_inv_range(smmu_domain, start, size, PAGE_SIZE, false);
142 }
143
arm_smmu_mm_release(struct mmu_notifier * mn,struct mm_struct * mm)144 static void arm_smmu_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
145 {
146 struct arm_smmu_domain *smmu_domain =
147 container_of(mn, struct arm_smmu_domain, mmu_notifier);
148 struct arm_smmu_master_domain *master_domain;
149 unsigned long flags;
150
151 /*
152 * DMA may still be running. Keep the cd valid to avoid C_BAD_CD events,
153 * but disable translation.
154 */
155 spin_lock_irqsave(&smmu_domain->devices_lock, flags);
156 list_for_each_entry(master_domain, &smmu_domain->devices,
157 devices_elm) {
158 struct arm_smmu_master *master = master_domain->master;
159 struct arm_smmu_cd target;
160 struct arm_smmu_cd *cdptr;
161
162 cdptr = arm_smmu_get_cd_ptr(master, master_domain->ssid);
163 if (WARN_ON(!cdptr))
164 continue;
165 arm_smmu_make_sva_cd(&target, master, NULL,
166 smmu_domain->cd.asid);
167 arm_smmu_write_cd_entry(master, master_domain->ssid, cdptr,
168 &target);
169 }
170 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags);
171
172 arm_smmu_domain_inv(smmu_domain);
173 }
174
arm_smmu_mmu_notifier_free(struct mmu_notifier * mn)175 static void arm_smmu_mmu_notifier_free(struct mmu_notifier *mn)
176 {
177 arm_smmu_domain_free(
178 container_of(mn, struct arm_smmu_domain, mmu_notifier));
179 }
180
181 static const struct mmu_notifier_ops arm_smmu_mmu_notifier_ops = {
182 .arch_invalidate_secondary_tlbs = arm_smmu_mm_arch_invalidate_secondary_tlbs,
183 .release = arm_smmu_mm_release,
184 .free_notifier = arm_smmu_mmu_notifier_free,
185 };
186
arm_smmu_sva_supported(struct arm_smmu_device * smmu)187 bool arm_smmu_sva_supported(struct arm_smmu_device *smmu)
188 {
189 unsigned long reg, fld;
190 unsigned long oas;
191 unsigned long asid_bits;
192 u32 feat_mask = ARM_SMMU_FEAT_COHERENCY;
193
194 if (vabits_actual == 52) {
195 /* We don't support LPA2 */
196 if (PAGE_SIZE != SZ_64K)
197 return false;
198 feat_mask |= ARM_SMMU_FEAT_VAX;
199 }
200
201 if (system_supports_bbml2_noabort())
202 feat_mask |= ARM_SMMU_FEAT_BBML2;
203
204 if ((smmu->features & feat_mask) != feat_mask)
205 return false;
206
207 if (!(smmu->pgsize_bitmap & PAGE_SIZE))
208 return false;
209
210 /*
211 * Get the smallest PA size of all CPUs (sanitized by cpufeature). We're
212 * not even pretending to support AArch32 here. Abort if the MMU outputs
213 * addresses larger than what we support.
214 */
215 reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
216 fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_EL1_PARANGE_SHIFT);
217 oas = id_aa64mmfr0_parange_to_phys_shift(fld);
218 if (smmu->oas < oas)
219 return false;
220
221 /* We can support bigger ASIDs than the CPU, but not smaller */
222 fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT);
223 asid_bits = fld ? 16 : 8;
224 if (smmu->asid_bits < asid_bits)
225 return false;
226
227 /*
228 * See max_pinned_asids in arch/arm64/mm/context.c. The following is
229 * generally the maximum number of bindable processes.
230 */
231 if (arm64_kernel_unmapped_at_el0())
232 asid_bits--;
233 dev_dbg(smmu->dev, "%d shared contexts\n", (1 << asid_bits) -
234 num_possible_cpus() - 2);
235
236 return true;
237 }
238
arm_smmu_sva_notifier_synchronize(void)239 void arm_smmu_sva_notifier_synchronize(void)
240 {
241 /*
242 * Some MMU notifiers may still be waiting to be freed, using
243 * arm_smmu_mmu_notifier_free(). Wait for them.
244 */
245 mmu_notifier_synchronize();
246 }
247
arm_smmu_sva_set_dev_pasid(struct iommu_domain * domain,struct device * dev,ioasid_t id,struct iommu_domain * old)248 static int arm_smmu_sva_set_dev_pasid(struct iommu_domain *domain,
249 struct device *dev, ioasid_t id,
250 struct iommu_domain *old)
251 {
252 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
253 struct arm_smmu_master *master = dev_iommu_priv_get(dev);
254 struct arm_smmu_cd target;
255 int ret;
256
257 if (!(master->smmu->features & ARM_SMMU_FEAT_SVA))
258 return -EOPNOTSUPP;
259
260 /* Prevent arm_smmu_mm_release from being called while we are attaching */
261 if (!mmget_not_zero(domain->mm))
262 return -EINVAL;
263
264 /*
265 * This does not need the arm_smmu_asid_lock because SVA domains never
266 * get reassigned
267 */
268 arm_smmu_make_sva_cd(&target, master, domain->mm, smmu_domain->cd.asid);
269 ret = arm_smmu_set_pasid(master, smmu_domain, id, &target, old);
270
271 mmput(domain->mm);
272 return ret;
273 }
274
arm_smmu_sva_domain_free(struct iommu_domain * domain)275 static void arm_smmu_sva_domain_free(struct iommu_domain *domain)
276 {
277 struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
278
279 /*
280 * Ensure the ASID is empty in the iommu cache before allowing reuse.
281 */
282 arm_smmu_domain_inv(smmu_domain);
283
284 /*
285 * Notice that the arm_smmu_mm_arch_invalidate_secondary_tlbs op can
286 * still be called/running at this point. We allow the ASID to be
287 * reused, and if there is a race then it just suffers harmless
288 * unnecessary invalidation.
289 */
290 xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid);
291
292 /*
293 * Actual free is defered to the SRCU callback
294 * arm_smmu_mmu_notifier_free()
295 */
296 mmu_notifier_put(&smmu_domain->mmu_notifier);
297 }
298
299 static const struct iommu_domain_ops arm_smmu_sva_domain_ops = {
300 .set_dev_pasid = arm_smmu_sva_set_dev_pasid,
301 .free = arm_smmu_sva_domain_free
302 };
303
arm_smmu_sva_domain_alloc(struct device * dev,struct mm_struct * mm)304 struct iommu_domain *arm_smmu_sva_domain_alloc(struct device *dev,
305 struct mm_struct *mm)
306 {
307 struct arm_smmu_master *master = dev_iommu_priv_get(dev);
308 struct arm_smmu_device *smmu = master->smmu;
309 struct arm_smmu_domain *smmu_domain;
310 u32 asid;
311 int ret;
312
313 if (!(master->smmu->features & ARM_SMMU_FEAT_SVA))
314 return ERR_PTR(-EOPNOTSUPP);
315
316 smmu_domain = arm_smmu_domain_alloc();
317 if (IS_ERR(smmu_domain))
318 return ERR_CAST(smmu_domain);
319 smmu_domain->domain.type = IOMMU_DOMAIN_SVA;
320 smmu_domain->domain.ops = &arm_smmu_sva_domain_ops;
321
322 /*
323 * Choose page_size as the leaf page size for invalidation when
324 * ARM_SMMU_FEAT_RANGE_INV is present
325 */
326 smmu_domain->domain.pgsize_bitmap = PAGE_SIZE;
327 smmu_domain->stage = ARM_SMMU_DOMAIN_SVA;
328 smmu_domain->smmu = smmu;
329
330 ret = xa_alloc(&arm_smmu_asid_xa, &asid, smmu_domain,
331 XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL);
332 if (ret)
333 goto err_free;
334
335 smmu_domain->cd.asid = asid;
336 smmu_domain->mmu_notifier.ops = &arm_smmu_mmu_notifier_ops;
337 ret = mmu_notifier_register(&smmu_domain->mmu_notifier, mm);
338 if (ret)
339 goto err_asid;
340
341 return &smmu_domain->domain;
342
343 err_asid:
344 xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid);
345 err_free:
346 arm_smmu_domain_free(smmu_domain);
347 return ERR_PTR(ret);
348 }
349