1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /**
3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
4 *
5 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
6 *
7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
8 */
9
10 #include <linux/stmmac.h>
11 #include <linux/hw_bitfield.h>
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/phy.h>
15 #include <linux/of_net.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/delay.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/regmap.h>
23 #include <linux/pm_runtime.h>
24
25 #include "stmmac_platform.h"
26
27 struct rk_priv_data;
28
29 struct rk_clock_fields {
30 /* io_clksel_cru_mask - io_clksel bit in clock GRF register which,
31 * when set, selects the tx clock from CRU.
32 */
33 u16 io_clksel_cru_mask;
34 /* io_clksel_io_mask - io_clksel bit in clock GRF register which,
35 * when set, selects the tx clock from IO.
36 */
37 u16 io_clksel_io_mask;
38 u16 gmii_clk_sel_mask;
39 u16 rmii_clk_sel_mask;
40 u16 rmii_gate_en_mask;
41 u16 rmii_mode_mask;
42 u16 mac_speed_mask;
43 };
44
45 struct rk_gmac_ops {
46 int (*init)(struct rk_priv_data *bsp_priv);
47 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
48 int tx_delay, int rx_delay);
49 void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
50 int (*set_speed)(struct rk_priv_data *bsp_priv,
51 phy_interface_t interface, int speed);
52 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
53 void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv);
54
55 u16 gmac_grf_reg;
56 u16 gmac_phy_intf_sel_mask;
57 u16 gmac_rmii_mode_mask;
58
59 u16 clock_grf_reg;
60 struct rk_clock_fields clock;
61
62 bool gmac_grf_reg_in_php;
63 bool clock_grf_reg_in_php;
64 bool supports_rgmii;
65 bool supports_rmii;
66 bool php_grf_required;
67 bool regs_valid;
68 u32 regs[];
69 };
70
71 static const char * const rk_clocks[] = {
72 "aclk_mac", "pclk_mac", "mac_clk_tx", "clk_mac_speed",
73 };
74
75 static const char * const rk_rmii_clocks[] = {
76 "mac_clk_rx", "clk_mac_ref", "clk_mac_refout",
77 };
78
79 enum rk_clocks_index {
80 RK_ACLK_MAC = 0,
81 RK_PCLK_MAC,
82 RK_MAC_CLK_TX,
83 RK_CLK_MAC_SPEED,
84 RK_MAC_CLK_RX,
85 RK_CLK_MAC_REF,
86 RK_CLK_MAC_REFOUT,
87 };
88
89 struct rk_priv_data {
90 struct device *dev;
91 phy_interface_t phy_iface;
92 int id;
93 struct regulator *regulator;
94 const struct rk_gmac_ops *ops;
95
96 bool clk_enabled;
97 bool clock_input;
98 bool integrated_phy;
99 bool supports_rgmii;
100 bool supports_rmii;
101
102 struct clk_bulk_data *clks;
103 int num_clks;
104 struct clk *clk_phy;
105
106 struct reset_control *phy_reset;
107
108 int tx_delay;
109 int rx_delay;
110
111 struct regmap *grf;
112 struct regmap *php_grf;
113
114 u16 gmac_grf_reg;
115 u16 gmac_phy_intf_sel_mask;
116 u16 gmac_rmii_mode_mask;
117
118 u16 clock_grf_reg;
119 struct rk_clock_fields clock;
120 };
121
122 #define GMAC_CLK_DIV1_125M 0
123 #define GMAC_CLK_DIV50_2_5M 2
124 #define GMAC_CLK_DIV5_25M 3
125
rk_gmac_rgmii_clk_div(int speed)126 static int rk_gmac_rgmii_clk_div(int speed)
127 {
128 if (speed == SPEED_10)
129 return GMAC_CLK_DIV50_2_5M;
130 if (speed == SPEED_100)
131 return GMAC_CLK_DIV5_25M;
132 if (speed == SPEED_1000)
133 return GMAC_CLK_DIV1_125M;
134 return -EINVAL;
135 }
136
rk_get_phy_intf_sel(phy_interface_t interface)137 static int rk_get_phy_intf_sel(phy_interface_t interface)
138 {
139 int ret = stmmac_get_phy_intf_sel(interface);
140
141 /* Only RGMII and RMII are supported */
142 if (ret != PHY_INTF_SEL_RGMII && ret != PHY_INTF_SEL_RMII)
143 ret = -EINVAL;
144
145 return ret;
146 }
147
rk_encode_wm16(u16 val,u16 mask)148 static u32 rk_encode_wm16(u16 val, u16 mask)
149 {
150 u32 reg_val = mask << 16;
151
152 if (mask)
153 reg_val |= mask & (val << (ffs(mask) - 1));
154
155 return reg_val;
156 }
157
rk_write_gmac_grf_reg(struct rk_priv_data * bsp_priv,u32 val)158 static int rk_write_gmac_grf_reg(struct rk_priv_data *bsp_priv, u32 val)
159 {
160 struct regmap *regmap;
161
162 if (bsp_priv->ops->gmac_grf_reg_in_php)
163 regmap = bsp_priv->php_grf;
164 else
165 regmap = bsp_priv->grf;
166
167 return regmap_write(regmap, bsp_priv->gmac_grf_reg, val);
168 }
169
rk_write_clock_grf_reg(struct rk_priv_data * bsp_priv,u32 val)170 static int rk_write_clock_grf_reg(struct rk_priv_data *bsp_priv, u32 val)
171 {
172 struct regmap *regmap;
173
174 if (bsp_priv->ops->clock_grf_reg_in_php)
175 regmap = bsp_priv->php_grf;
176 else
177 regmap = bsp_priv->grf;
178
179 return regmap_write(regmap, bsp_priv->clock_grf_reg, val);
180 }
181
rk_set_rmii_gate_en(struct rk_priv_data * bsp_priv,bool state)182 static int rk_set_rmii_gate_en(struct rk_priv_data *bsp_priv, bool state)
183 {
184 u32 val;
185
186 if (!bsp_priv->clock.rmii_gate_en_mask)
187 return 0;
188
189 val = rk_encode_wm16(state, bsp_priv->clock.rmii_gate_en_mask);
190
191 return rk_write_clock_grf_reg(bsp_priv, val);
192 }
193
rk_ungate_rmii_clock(struct rk_priv_data * bsp_priv)194 static int rk_ungate_rmii_clock(struct rk_priv_data *bsp_priv)
195 {
196 return rk_set_rmii_gate_en(bsp_priv, false);
197 }
198
rk_gate_rmii_clock(struct rk_priv_data * bsp_priv)199 static int rk_gate_rmii_clock(struct rk_priv_data *bsp_priv)
200 {
201 return rk_set_rmii_gate_en(bsp_priv, true);
202 }
203
rk_configure_io_clksel(struct rk_priv_data * bsp_priv)204 static int rk_configure_io_clksel(struct rk_priv_data *bsp_priv)
205 {
206 bool io, cru;
207 u32 val;
208
209 if (!bsp_priv->clock.io_clksel_io_mask &&
210 !bsp_priv->clock.io_clksel_cru_mask)
211 return 0;
212
213 io = bsp_priv->clock_input;
214 cru = !io;
215
216 /* The io_clksel configuration can be either:
217 * 0=CRU, 1=IO (rk3506, rk3528, rk3576) or
218 * 0=IO, 1=CRU (rk3588)
219 * where CRU means the transmit clock comes from the CRU and IO
220 * means the transmit clock comes from IO.
221 *
222 * Handle this by having two masks.
223 */
224 val = rk_encode_wm16(io, bsp_priv->clock.io_clksel_io_mask) |
225 rk_encode_wm16(cru, bsp_priv->clock.io_clksel_cru_mask);
226
227 return rk_write_clock_grf_reg(bsp_priv, val);
228 }
229
rk_set_clk_mac_speed(struct rk_priv_data * bsp_priv,phy_interface_t interface,int speed)230 static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv,
231 phy_interface_t interface, int speed)
232 {
233 struct clk *clk_mac_speed = bsp_priv->clks[RK_CLK_MAC_SPEED].clk;
234 long rate;
235
236 rate = rgmii_clock(speed);
237 if (rate < 0)
238 return rate;
239
240 return clk_set_rate(clk_mac_speed, rate);
241 }
242
243 #define GRF_FIELD(hi, lo, val) \
244 FIELD_PREP_WM16(GENMASK_U16(hi, lo), val)
245
246 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
247 #define GRF_CLR_BIT(nr) (BIT(nr+16))
248
249 #define DELAY_ENABLE(soc, tx, rx) \
250 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
251 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
252
253 #define RK_GRF_MACPHY_CON0 0xb00
254 #define RK_MACPHY_ENABLE GRF_BIT(0)
255 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
256 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
257 #define RK_GMAC2PHY_RMII_MODE GRF_FIELD(7, 6, 1)
258
259 #define RK_GRF_MACPHY_CON1 0xb04
260
261 #define RK_GRF_MACPHY_CON2 0xb08
262 #define RK_GRF_CON2_MACPHY_ID GRF_FIELD(15, 0, 0x1234)
263
264 #define RK_GRF_MACPHY_CON3 0xb0c
265 #define RK_GRF_CON3_MACPHY_ID GRF_FIELD(5, 0, 0x35)
266
rk_gmac_integrated_ephy_powerup(struct rk_priv_data * priv)267 static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)
268 {
269 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
270 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
271
272 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
273 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
274
275 if (priv->phy_reset) {
276 /* PHY needs to be disabled before trying to reset it */
277 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
278 if (priv->phy_reset)
279 reset_control_assert(priv->phy_reset);
280 usleep_range(10, 20);
281 if (priv->phy_reset)
282 reset_control_deassert(priv->phy_reset);
283 usleep_range(10, 20);
284 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
285 msleep(30);
286 }
287 }
288
rk_gmac_integrated_ephy_powerdown(struct rk_priv_data * priv)289 static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv)
290 {
291 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
292 if (priv->phy_reset)
293 reset_control_assert(priv->phy_reset);
294 }
295
296 #define RK_FEPHY_SHUTDOWN GRF_BIT(1)
297 #define RK_FEPHY_POWERUP GRF_CLR_BIT(1)
298 #define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6)
299 #define RK_FEPHY_24M_CLK_SEL GRF_FIELD(9, 8, 3)
300 #define RK_FEPHY_PHY_ID GRF_BIT(11)
301
rk_gmac_integrated_fephy_powerup(struct rk_priv_data * priv,unsigned int reg)302 static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv,
303 unsigned int reg)
304 {
305 reset_control_assert(priv->phy_reset);
306 usleep_range(20, 30);
307
308 regmap_write(priv->grf, reg,
309 RK_FEPHY_POWERUP |
310 RK_FEPHY_INTERNAL_RMII_SEL |
311 RK_FEPHY_24M_CLK_SEL |
312 RK_FEPHY_PHY_ID);
313 usleep_range(10000, 12000);
314
315 reset_control_deassert(priv->phy_reset);
316 usleep_range(50000, 60000);
317 }
318
rk_gmac_integrated_fephy_powerdown(struct rk_priv_data * priv,unsigned int reg)319 static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
320 unsigned int reg)
321 {
322 regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN);
323 }
324
325 #define PX30_GRF_GMAC_CON1 0x0904
326
327 static const struct rk_gmac_ops px30_ops = {
328 .set_speed = rk_set_clk_mac_speed,
329
330 .gmac_grf_reg = PX30_GRF_GMAC_CON1,
331 .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
332
333 .clock_grf_reg = PX30_GRF_GMAC_CON1,
334 .clock.mac_speed_mask = BIT_U16(2),
335
336 .supports_rmii = true,
337 };
338
339 #define RK3128_GRF_MAC_CON0 0x0168
340 #define RK3128_GRF_MAC_CON1 0x016c
341
342 /* RK3128_GRF_MAC_CON0 */
343 #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
344 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
345 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
346 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
347 #define RK3128_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val)
348 #define RK3128_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
349
350 /* RK3128_GRF_MAC_CON1 */
351 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
352 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
353
rk3128_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)354 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
355 int tx_delay, int rx_delay)
356 {
357 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
358 DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
359 RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
360 RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
361 }
362
363 static const struct rk_gmac_ops rk3128_ops = {
364 .set_to_rgmii = rk3128_set_to_rgmii,
365
366 .gmac_grf_reg = RK3128_GRF_MAC_CON1,
367 .gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
368 .gmac_rmii_mode_mask = BIT_U16(14),
369
370 .clock_grf_reg = RK3128_GRF_MAC_CON1,
371 .clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
372 .clock.rmii_clk_sel_mask = BIT_U16(11),
373 .clock.mac_speed_mask = BIT_U16(10),
374
375 .supports_rmii = true,
376 };
377
378 #define RK3228_GRF_MAC_CON0 0x0900
379 #define RK3228_GRF_MAC_CON1 0x0904
380
381 #define RK3228_GRF_CON_MUX 0x50
382
383 /* RK3228_GRF_MAC_CON0 */
384 #define RK3228_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val)
385 #define RK3228_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
386
387 /* RK3228_GRF_MAC_CON1 */
388 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
389 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
390 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
391 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
392 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
393 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
394
395 /* RK3228_GRF_COM_MUX */
396 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15)
397
rk3228_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)398 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
399 int tx_delay, int rx_delay)
400 {
401 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
402 DELAY_ENABLE(RK3228, tx_delay, rx_delay));
403
404 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
405 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
406 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
407 }
408
rk3228_set_to_rmii(struct rk_priv_data * bsp_priv)409 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
410 {
411 /* set MAC to RMII mode */
412 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
413 }
414
rk3228_integrated_phy_powerup(struct rk_priv_data * priv)415 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
416 {
417 regmap_write(priv->grf, RK3228_GRF_CON_MUX,
418 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
419
420 rk_gmac_integrated_ephy_powerup(priv);
421 }
422
423 static const struct rk_gmac_ops rk3228_ops = {
424 .set_to_rgmii = rk3228_set_to_rgmii,
425 .set_to_rmii = rk3228_set_to_rmii,
426 .integrated_phy_powerup = rk3228_integrated_phy_powerup,
427 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
428
429 .gmac_grf_reg = RK3228_GRF_MAC_CON1,
430 .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
431 .gmac_rmii_mode_mask = BIT_U16(10),
432
433 .clock_grf_reg = RK3228_GRF_MAC_CON1,
434 .clock.gmii_clk_sel_mask = GENMASK_U16(9, 8),
435 .clock.rmii_clk_sel_mask = BIT_U16(7),
436 .clock.mac_speed_mask = BIT_U16(2),
437 };
438
439 #define RK3288_GRF_SOC_CON1 0x0248
440 #define RK3288_GRF_SOC_CON3 0x0250
441
442 /*RK3288_GRF_SOC_CON1*/
443 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
444 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
445
446 /*RK3288_GRF_SOC_CON3*/
447 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
448 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
449 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
450 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
451 #define RK3288_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val)
452 #define RK3288_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
453
rk3288_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)454 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
455 int tx_delay, int rx_delay)
456 {
457 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
458 DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
459 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
460 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
461 }
462
463 static const struct rk_gmac_ops rk3288_ops = {
464 .set_to_rgmii = rk3288_set_to_rgmii,
465
466 .gmac_grf_reg = RK3288_GRF_SOC_CON1,
467 .gmac_phy_intf_sel_mask = GENMASK_U16(8, 6),
468 .gmac_rmii_mode_mask = BIT_U16(14),
469
470 .clock_grf_reg = RK3288_GRF_SOC_CON1,
471 .clock.gmii_clk_sel_mask = GENMASK_U16(13, 12),
472 .clock.rmii_clk_sel_mask = BIT_U16(11),
473 .clock.mac_speed_mask = BIT_U16(10),
474
475 .supports_rmii = true,
476 };
477
478 #define RK3308_GRF_MAC_CON0 0x04a0
479
480 /* RK3308_GRF_MAC_CON0 */
481 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
482 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
483
484 static const struct rk_gmac_ops rk3308_ops = {
485 .gmac_grf_reg = RK3308_GRF_MAC_CON0,
486 .gmac_phy_intf_sel_mask = GENMASK_U16(4, 2),
487
488 .clock_grf_reg = RK3308_GRF_MAC_CON0,
489 .clock.mac_speed_mask = BIT_U16(0),
490
491 .supports_rmii = true,
492 };
493
494 #define RK3328_GRF_MAC_CON0 0x0900
495 #define RK3328_GRF_MAC_CON1 0x0904
496 #define RK3328_GRF_MAC_CON2 0x0908
497 #define RK3328_GRF_MACPHY_CON1 0xb04
498
499 /* RK3328_GRF_MAC_CON0 */
500 #define RK3328_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(13, 7, val)
501 #define RK3328_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
502
503 /* RK3328_GRF_MAC_CON1 */
504 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
505 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
506 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
507 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
508
509 /* RK3328_GRF_MACPHY_CON1 */
510 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9)
511
rk3328_init(struct rk_priv_data * bsp_priv)512 static int rk3328_init(struct rk_priv_data *bsp_priv)
513 {
514 switch (bsp_priv->id) {
515 case 0: /* gmac2io */
516 bsp_priv->gmac_grf_reg = RK3328_GRF_MAC_CON1;
517 bsp_priv->clock_grf_reg = RK3328_GRF_MAC_CON1;
518 bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(12, 11);
519 return 0;
520
521 case 1: /* gmac2phy */
522 bsp_priv->gmac_grf_reg = RK3328_GRF_MAC_CON2;
523 bsp_priv->clock_grf_reg = RK3328_GRF_MAC_CON2;
524 bsp_priv->supports_rgmii = false;
525 return 0;
526
527 default:
528 return -EINVAL;
529 }
530 }
531
rk3328_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)532 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
533 int tx_delay, int rx_delay)
534 {
535 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
536 RK3328_GMAC_RXCLK_DLY_ENABLE |
537 RK3328_GMAC_TXCLK_DLY_ENABLE);
538
539 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
540 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
541 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
542 }
543
rk3328_integrated_phy_powerup(struct rk_priv_data * priv)544 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
545 {
546 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
547 RK3328_MACPHY_RMII_MODE);
548
549 rk_gmac_integrated_ephy_powerup(priv);
550 }
551
552 static const struct rk_gmac_ops rk3328_ops = {
553 .init = rk3328_init,
554 .set_to_rgmii = rk3328_set_to_rgmii,
555 .integrated_phy_powerup = rk3328_integrated_phy_powerup,
556 .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
557
558 .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
559 .gmac_rmii_mode_mask = BIT_U16(9),
560
561 .clock.rmii_clk_sel_mask = BIT_U16(7),
562 .clock.mac_speed_mask = BIT_U16(2),
563
564 .supports_rmii = true,
565
566 .regs_valid = true,
567 .regs = {
568 0xff540000, /* gmac2io */
569 0xff550000, /* gmac2phy */
570 0, /* sentinel */
571 },
572 };
573
574 #define RK3366_GRF_SOC_CON6 0x0418
575 #define RK3366_GRF_SOC_CON7 0x041c
576
577 /* RK3366_GRF_SOC_CON6 */
578 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
579 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
580
581 /* RK3366_GRF_SOC_CON7 */
582 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
583 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
584 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
585 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
586 #define RK3366_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
587 #define RK3366_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
588
rk3366_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)589 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
590 int tx_delay, int rx_delay)
591 {
592 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
593 DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
594 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
595 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
596 }
597
598 static const struct rk_gmac_ops rk3366_ops = {
599 .set_to_rgmii = rk3366_set_to_rgmii,
600
601 .gmac_grf_reg = RK3366_GRF_SOC_CON6,
602 .gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
603 .gmac_rmii_mode_mask = BIT_U16(6),
604
605 .clock_grf_reg = RK3366_GRF_SOC_CON6,
606 .clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
607 .clock.rmii_clk_sel_mask = BIT_U16(3),
608 .clock.mac_speed_mask = BIT_U16(7),
609
610 .supports_rmii = true,
611 };
612
613 #define RK3368_GRF_SOC_CON15 0x043c
614 #define RK3368_GRF_SOC_CON16 0x0440
615
616 /* RK3368_GRF_SOC_CON15 */
617 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
618 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
619
620 /* RK3368_GRF_SOC_CON16 */
621 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
622 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
623 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
624 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
625 #define RK3368_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
626 #define RK3368_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
627
rk3368_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)628 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
629 int tx_delay, int rx_delay)
630 {
631 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
632 DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
633 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
634 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
635 }
636
637 static const struct rk_gmac_ops rk3368_ops = {
638 .set_to_rgmii = rk3368_set_to_rgmii,
639
640 .gmac_grf_reg = RK3368_GRF_SOC_CON15,
641 .gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
642 .gmac_rmii_mode_mask = BIT_U16(6),
643
644 .clock_grf_reg = RK3368_GRF_SOC_CON15,
645 .clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
646 .clock.rmii_clk_sel_mask = BIT_U16(3),
647 .clock.mac_speed_mask = BIT_U16(7),
648
649 .supports_rmii = true,
650 };
651
652 #define RK3399_GRF_SOC_CON5 0xc214
653 #define RK3399_GRF_SOC_CON6 0xc218
654
655 /* RK3399_GRF_SOC_CON5 */
656 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
657 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
658
659 /* RK3399_GRF_SOC_CON6 */
660 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
661 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
662 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
663 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
664 #define RK3399_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
665 #define RK3399_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
666
rk3399_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)667 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
668 int tx_delay, int rx_delay)
669 {
670 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
671 DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
672 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
673 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
674 }
675
676 static const struct rk_gmac_ops rk3399_ops = {
677 .set_to_rgmii = rk3399_set_to_rgmii,
678
679 .gmac_grf_reg = RK3399_GRF_SOC_CON5,
680 .gmac_phy_intf_sel_mask = GENMASK_U16(11, 9),
681 .gmac_rmii_mode_mask = BIT_U16(6),
682
683 .clock_grf_reg = RK3399_GRF_SOC_CON5,
684 .clock.gmii_clk_sel_mask = GENMASK_U16(5, 4),
685 .clock.rmii_clk_sel_mask = BIT_U16(3),
686 .clock.mac_speed_mask = BIT_U16(7),
687
688 .supports_rmii = true,
689 };
690
691 #define RK3506_GRF_SOC_CON8 0x0020
692 #define RK3506_GRF_SOC_CON11 0x002c
693
694 #define RK3506_GMAC_RMII_MODE GRF_BIT(1)
695
rk3506_init(struct rk_priv_data * bsp_priv)696 static int rk3506_init(struct rk_priv_data *bsp_priv)
697 {
698 switch (bsp_priv->id) {
699 case 0:
700 bsp_priv->clock_grf_reg = RK3506_GRF_SOC_CON8;
701 return 0;
702
703 case 1:
704 bsp_priv->clock_grf_reg = RK3506_GRF_SOC_CON11;
705 return 0;
706
707 default:
708 return -EINVAL;
709 }
710 }
711
712 static const struct rk_gmac_ops rk3506_ops = {
713 .init = rk3506_init,
714
715 .clock.io_clksel_io_mask = BIT_U16(5),
716 .clock.rmii_clk_sel_mask = BIT_U16(3),
717 .clock.rmii_gate_en_mask = BIT_U16(2),
718 .clock.rmii_mode_mask = BIT_U16(1),
719
720 .supports_rmii = true,
721
722 .regs_valid = true,
723 .regs = {
724 0xff4c8000, /* gmac0 */
725 0xff4d0000, /* gmac1 */
726 0x0, /* sentinel */
727 },
728 };
729
730 #define RK3528_VO_GRF_GMAC_CON 0x0018
731 #define RK3528_VO_GRF_MACPHY_CON0 0x001c
732 #define RK3528_VO_GRF_MACPHY_CON1 0x0020
733 #define RK3528_VPU_GRF_GMAC_CON5 0x0018
734 #define RK3528_VPU_GRF_GMAC_CON6 0x001c
735
736 #define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
737 #define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
738 #define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
739 #define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
740
741 #define RK3528_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(15, 8, val)
742 #define RK3528_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(7, 0, val)
743
rk3528_init(struct rk_priv_data * bsp_priv)744 static int rk3528_init(struct rk_priv_data *bsp_priv)
745 {
746 switch (bsp_priv->id) {
747 case 0:
748 bsp_priv->clock_grf_reg = RK3528_VO_GRF_GMAC_CON;
749 bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(3);
750 bsp_priv->clock.rmii_gate_en_mask = BIT_U16(2);
751 bsp_priv->clock.rmii_mode_mask = BIT_U16(1);
752 bsp_priv->supports_rgmii = false;
753 return 0;
754
755 case 1:
756 bsp_priv->clock_grf_reg = RK3528_VPU_GRF_GMAC_CON5;
757 bsp_priv->clock.io_clksel_io_mask = BIT_U16(12);
758 bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(11, 10);
759 bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(10);
760 bsp_priv->clock.rmii_gate_en_mask = BIT_U16(9);
761 bsp_priv->clock.rmii_mode_mask = BIT_U16(8);
762 return 0;
763
764 default:
765 return -EINVAL;
766 }
767 }
768
rk3528_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)769 static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
770 int tx_delay, int rx_delay)
771 {
772 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
773 DELAY_ENABLE(RK3528, tx_delay, rx_delay));
774
775 regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,
776 RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
777 RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
778 }
779
rk3528_integrated_phy_powerup(struct rk_priv_data * bsp_priv)780 static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv)
781 {
782 rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);
783 }
784
rk3528_integrated_phy_powerdown(struct rk_priv_data * bsp_priv)785 static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv)
786 {
787 rk_gmac_integrated_fephy_powerdown(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);
788 }
789
790 static const struct rk_gmac_ops rk3528_ops = {
791 .init = rk3528_init,
792 .set_to_rgmii = rk3528_set_to_rgmii,
793 .integrated_phy_powerup = rk3528_integrated_phy_powerup,
794 .integrated_phy_powerdown = rk3528_integrated_phy_powerdown,
795
796 .supports_rmii = true,
797
798 .regs_valid = true,
799 .regs = {
800 0xffbd0000, /* gmac0 */
801 0xffbe0000, /* gmac1 */
802 0x0, /* sentinel */
803 },
804 };
805
806 #define RK3568_GRF_GMAC0_CON0 0x0380
807 #define RK3568_GRF_GMAC0_CON1 0x0384
808 #define RK3568_GRF_GMAC1_CON0 0x0388
809 #define RK3568_GRF_GMAC1_CON1 0x038c
810
811 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
812 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
813 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
814 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
815 #define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
816 #define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
817 #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
818
819 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
820 #define RK3568_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
821 #define RK3568_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
822
rk3568_init(struct rk_priv_data * bsp_priv)823 static int rk3568_init(struct rk_priv_data *bsp_priv)
824 {
825 switch (bsp_priv->id) {
826 case 0:
827 bsp_priv->gmac_grf_reg = RK3568_GRF_GMAC0_CON1;
828 return 0;
829
830 case 1:
831 bsp_priv->gmac_grf_reg = RK3568_GRF_GMAC1_CON1;
832 return 0;
833
834 default:
835 return -EINVAL;
836 }
837 }
838
rk3568_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)839 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
840 int tx_delay, int rx_delay)
841 {
842 u32 con0, con1;
843
844 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 :
845 RK3568_GRF_GMAC0_CON0;
846 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
847 RK3568_GRF_GMAC0_CON1;
848
849 regmap_write(bsp_priv->grf, con0,
850 RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
851 RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
852
853 regmap_write(bsp_priv->grf, con1,
854 RK3568_GMAC_RXCLK_DLY_ENABLE |
855 RK3568_GMAC_TXCLK_DLY_ENABLE);
856 }
857
858 static const struct rk_gmac_ops rk3568_ops = {
859 .init = rk3568_init,
860 .set_to_rgmii = rk3568_set_to_rgmii,
861 .set_speed = rk_set_clk_mac_speed,
862
863 .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
864
865 .supports_rmii = true,
866
867 .regs_valid = true,
868 .regs = {
869 0xfe2a0000, /* gmac0 */
870 0xfe010000, /* gmac1 */
871 0x0, /* sentinel */
872 },
873 };
874
875 /* VCCIO0_1_3_IOC */
876 #define RK3576_VCCIO0_1_3_IOC_CON2 0X6408
877 #define RK3576_VCCIO0_1_3_IOC_CON3 0X640c
878 #define RK3576_VCCIO0_1_3_IOC_CON4 0X6410
879 #define RK3576_VCCIO0_1_3_IOC_CON5 0X6414
880
881 #define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
882 #define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
883 #define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
884 #define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
885
886 #define RK3576_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
887 #define RK3576_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
888
889 /* SDGMAC_GRF */
890 #define RK3576_GRF_GMAC_CON0 0X0020
891 #define RK3576_GRF_GMAC_CON1 0X0024
892
rk3576_init(struct rk_priv_data * bsp_priv)893 static int rk3576_init(struct rk_priv_data *bsp_priv)
894 {
895 switch (bsp_priv->id) {
896 case 0:
897 bsp_priv->gmac_grf_reg = RK3576_GRF_GMAC_CON0;
898 bsp_priv->clock_grf_reg = RK3576_GRF_GMAC_CON0;
899 return 0;
900
901 case 1:
902 bsp_priv->gmac_grf_reg = RK3576_GRF_GMAC_CON1;
903 bsp_priv->clock_grf_reg = RK3576_GRF_GMAC_CON1;
904 return 0;
905
906 default:
907 return -EINVAL;
908 }
909 }
910
rk3576_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)911 static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv,
912 int tx_delay, int rx_delay)
913 {
914 unsigned int offset_con;
915
916 offset_con = bsp_priv->id == 1 ? RK3576_VCCIO0_1_3_IOC_CON4 :
917 RK3576_VCCIO0_1_3_IOC_CON2;
918
919 /* m0 && m1 delay enabled */
920 regmap_write(bsp_priv->php_grf, offset_con,
921 DELAY_ENABLE(RK3576, tx_delay, rx_delay));
922 regmap_write(bsp_priv->php_grf, offset_con + 0x4,
923 DELAY_ENABLE(RK3576, tx_delay, rx_delay));
924
925 /* m0 && m1 delay value */
926 regmap_write(bsp_priv->php_grf, offset_con,
927 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) |
928 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
929 regmap_write(bsp_priv->php_grf, offset_con + 0x4,
930 RK3576_GMAC_CLK_TX_DL_CFG(tx_delay) |
931 RK3576_GMAC_CLK_RX_DL_CFG(rx_delay));
932 }
933
934 static const struct rk_gmac_ops rk3576_ops = {
935 .init = rk3576_init,
936 .set_to_rgmii = rk3576_set_to_rgmii,
937
938 .gmac_rmii_mode_mask = BIT_U16(3),
939
940 .clock.io_clksel_io_mask = BIT_U16(7),
941 .clock.gmii_clk_sel_mask = GENMASK_U16(6, 5),
942 .clock.rmii_clk_sel_mask = BIT_U16(5),
943 .clock.rmii_gate_en_mask = BIT_U16(4),
944
945 .supports_rmii = true,
946
947 .php_grf_required = true,
948 .regs_valid = true,
949 .regs = {
950 0x2a220000, /* gmac0 */
951 0x2a230000, /* gmac1 */
952 0x0, /* sentinel */
953 },
954 };
955
956 /* sys_grf */
957 #define RK3588_GRF_GMAC_CON7 0X031c
958 #define RK3588_GRF_GMAC_CON8 0X0320
959 #define RK3588_GRF_GMAC_CON9 0X0324
960
961 #define RK3588_GMAC_RXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 3)
962 #define RK3588_GMAC_RXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 3)
963 #define RK3588_GMAC_TXCLK_DLY_ENABLE(id) GRF_BIT(2 * (id) + 2)
964 #define RK3588_GMAC_TXCLK_DLY_DISABLE(id) GRF_CLR_BIT(2 * (id) + 2)
965
966 #define RK3588_GMAC_CLK_RX_DL_CFG(val) GRF_FIELD(15, 8, val)
967 #define RK3588_GMAC_CLK_TX_DL_CFG(val) GRF_FIELD(7, 0, val)
968
969 /* php_grf */
970 #define RK3588_GRF_GMAC_CON0 0X0008
971 #define RK3588_GRF_CLK_CON1 0X0070
972
rk3588_init(struct rk_priv_data * bsp_priv)973 static int rk3588_init(struct rk_priv_data *bsp_priv)
974 {
975 switch (bsp_priv->id) {
976 case 0:
977 bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(5, 3);
978 bsp_priv->clock.io_clksel_cru_mask = BIT_U16(4);
979 bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(3, 2);
980 bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(2);
981 bsp_priv->clock.rmii_gate_en_mask = BIT_U16(1);
982 bsp_priv->clock.rmii_mode_mask = BIT_U16(0);
983 return 0;
984
985 case 1:
986 bsp_priv->gmac_phy_intf_sel_mask = GENMASK_U16(11, 9);
987 bsp_priv->clock.io_clksel_cru_mask = BIT_U16(9);
988 bsp_priv->clock.gmii_clk_sel_mask = GENMASK_U16(8, 7);
989 bsp_priv->clock.rmii_clk_sel_mask = BIT_U16(7);
990 bsp_priv->clock.rmii_gate_en_mask = BIT_U16(6);
991 bsp_priv->clock.rmii_mode_mask = BIT_U16(5);
992 return 0;
993
994 default:
995 return -EINVAL;
996 }
997 }
998
rk3588_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)999 static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
1000 int tx_delay, int rx_delay)
1001 {
1002 u32 offset_con, id = bsp_priv->id;
1003
1004 offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 :
1005 RK3588_GRF_GMAC_CON8;
1006
1007 regmap_write(bsp_priv->grf, RK3588_GRF_GMAC_CON7,
1008 RK3588_GMAC_RXCLK_DLY_ENABLE(id) |
1009 RK3588_GMAC_TXCLK_DLY_ENABLE(id));
1010
1011 regmap_write(bsp_priv->grf, offset_con,
1012 RK3588_GMAC_CLK_RX_DL_CFG(rx_delay) |
1013 RK3588_GMAC_CLK_TX_DL_CFG(tx_delay));
1014 }
1015
1016 static const struct rk_gmac_ops rk3588_ops = {
1017 .init = rk3588_init,
1018 .set_to_rgmii = rk3588_set_to_rgmii,
1019
1020 .gmac_grf_reg_in_php = true,
1021 .gmac_grf_reg = RK3588_GRF_GMAC_CON0,
1022
1023 .clock_grf_reg_in_php = true,
1024 .clock_grf_reg = RK3588_GRF_CLK_CON1,
1025
1026 .supports_rmii = true,
1027
1028 .php_grf_required = true,
1029 .regs_valid = true,
1030 .regs = {
1031 0xfe1b0000, /* gmac0 */
1032 0xfe1c0000, /* gmac1 */
1033 0x0, /* sentinel */
1034 },
1035 };
1036
1037 #define RV1108_GRF_GMAC_CON0 0X0900
1038
1039 /* RV1108_GRF_GMAC_CON0 */
1040 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
1041 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
1042
1043 static const struct rk_gmac_ops rv1108_ops = {
1044 .gmac_grf_reg = RV1108_GRF_GMAC_CON0,
1045 .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
1046
1047 .clock_grf_reg = RV1108_GRF_GMAC_CON0,
1048 .clock.rmii_clk_sel_mask = BIT_U16(7),
1049 .clock.mac_speed_mask = BIT_U16(2),
1050
1051 .supports_rmii = true,
1052 };
1053
1054 #define RV1126_GRF_GMAC_CON0 0X0070
1055 #define RV1126_GRF_GMAC_CON1 0X0074
1056 #define RV1126_GRF_GMAC_CON2 0X0078
1057
1058 /* RV1126_GRF_GMAC_CON0 */
1059 #define RV1126_GMAC_FLOW_CTRL GRF_BIT(7)
1060 #define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7)
1061 #define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1)
1062 #define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
1063 #define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0)
1064 #define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
1065 #define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3)
1066 #define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3)
1067 #define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2)
1068 #define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2)
1069
1070 /* RV1126_GRF_GMAC_CON1 */
1071 #define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
1072 #define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
1073 /* RV1126_GRF_GMAC_CON2 */
1074 #define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) GRF_FIELD(14, 8, val)
1075 #define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) GRF_FIELD(6, 0, val)
1076
rv1126_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1077 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
1078 int tx_delay, int rx_delay)
1079 {
1080 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
1081 RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
1082 RV1126_GMAC_M0_TXCLK_DLY_ENABLE |
1083 RV1126_GMAC_M1_RXCLK_DLY_ENABLE |
1084 RV1126_GMAC_M1_TXCLK_DLY_ENABLE);
1085
1086 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1,
1087 RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) |
1088 RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay));
1089
1090 regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2,
1091 RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) |
1092 RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
1093 }
1094
1095 static const struct rk_gmac_ops rv1126_ops = {
1096 .set_to_rgmii = rv1126_set_to_rgmii,
1097 .set_speed = rk_set_clk_mac_speed,
1098
1099 .gmac_grf_reg = RV1126_GRF_GMAC_CON0,
1100 .gmac_phy_intf_sel_mask = GENMASK_U16(6, 4),
1101
1102 .supports_rmii = true,
1103 };
1104
rk_gmac_clk_init(struct plat_stmmacenet_data * plat)1105 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
1106 {
1107 struct rk_priv_data *bsp_priv = plat->bsp_priv;
1108 int phy_iface = bsp_priv->phy_iface;
1109 struct device *dev = bsp_priv->dev;
1110 int i, j, ret;
1111
1112 bsp_priv->clk_enabled = false;
1113
1114 bsp_priv->num_clks = ARRAY_SIZE(rk_clocks);
1115 if (phy_iface == PHY_INTERFACE_MODE_RMII)
1116 bsp_priv->num_clks += ARRAY_SIZE(rk_rmii_clocks);
1117
1118 bsp_priv->clks = devm_kcalloc(dev, bsp_priv->num_clks,
1119 sizeof(*bsp_priv->clks), GFP_KERNEL);
1120 if (!bsp_priv->clks)
1121 return -ENOMEM;
1122
1123 for (i = 0; i < ARRAY_SIZE(rk_clocks); i++)
1124 bsp_priv->clks[i].id = rk_clocks[i];
1125
1126 if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1127 for (j = 0; j < ARRAY_SIZE(rk_rmii_clocks); j++)
1128 bsp_priv->clks[i++].id = rk_rmii_clocks[j];
1129 }
1130
1131 ret = devm_clk_bulk_get_optional(dev, bsp_priv->num_clks,
1132 bsp_priv->clks);
1133 if (ret)
1134 return dev_err_probe(dev, ret, "Failed to get clocks\n");
1135
1136 if (bsp_priv->clock_input) {
1137 dev_info(dev, "clock input from PHY\n");
1138 } else if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1139 clk_set_rate(plat->stmmac_clk, 50000000);
1140 }
1141
1142 if (plat->phy_node && bsp_priv->integrated_phy) {
1143 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
1144 ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy);
1145 if (ret)
1146 return dev_err_probe(dev, ret, "Cannot get PHY clock\n");
1147 clk_set_rate(bsp_priv->clk_phy, 50000000);
1148 }
1149
1150 return 0;
1151 }
1152
gmac_clk_enable(struct rk_priv_data * bsp_priv,bool enable)1153 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
1154 {
1155 int ret;
1156
1157 if (enable) {
1158 if (!bsp_priv->clk_enabled) {
1159 ret = clk_bulk_prepare_enable(bsp_priv->num_clks,
1160 bsp_priv->clks);
1161 if (ret)
1162 return ret;
1163
1164 ret = clk_prepare_enable(bsp_priv->clk_phy);
1165 if (ret)
1166 return ret;
1167
1168 rk_configure_io_clksel(bsp_priv);
1169 rk_ungate_rmii_clock(bsp_priv);
1170
1171 mdelay(5);
1172 bsp_priv->clk_enabled = true;
1173 }
1174 } else {
1175 if (bsp_priv->clk_enabled) {
1176 rk_gate_rmii_clock(bsp_priv);
1177
1178 clk_bulk_disable_unprepare(bsp_priv->num_clks,
1179 bsp_priv->clks);
1180 clk_disable_unprepare(bsp_priv->clk_phy);
1181
1182 bsp_priv->clk_enabled = false;
1183 }
1184 }
1185
1186 return 0;
1187 }
1188
rk_phy_powerup(struct rk_priv_data * bsp_priv)1189 static int rk_phy_powerup(struct rk_priv_data *bsp_priv)
1190 {
1191 struct regulator *ldo = bsp_priv->regulator;
1192 int ret;
1193
1194 ret = regulator_enable(ldo);
1195 if (ret)
1196 dev_err(bsp_priv->dev, "fail to enable phy-supply\n");
1197
1198 return ret;
1199 }
1200
rk_phy_powerdown(struct rk_priv_data * bsp_priv)1201 static void rk_phy_powerdown(struct rk_priv_data *bsp_priv)
1202 {
1203 struct regulator *ldo = bsp_priv->regulator;
1204 int ret;
1205
1206 ret = regulator_disable(ldo);
1207 if (ret)
1208 dev_err(bsp_priv->dev, "fail to disable phy-supply\n");
1209 }
1210
rk_gmac_setup(struct platform_device * pdev,struct plat_stmmacenet_data * plat,const struct rk_gmac_ops * ops)1211 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
1212 struct plat_stmmacenet_data *plat,
1213 const struct rk_gmac_ops *ops)
1214 {
1215 struct rk_priv_data *bsp_priv;
1216 struct device *dev = &pdev->dev;
1217 struct resource *res;
1218 int ret;
1219 const char *strings = NULL;
1220 int value;
1221
1222 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
1223 if (!bsp_priv)
1224 return ERR_PTR(-ENOMEM);
1225
1226 bsp_priv->phy_iface = plat->phy_interface;
1227 bsp_priv->ops = ops;
1228
1229 /* Some SoCs have multiple MAC controllers, which need
1230 * to be distinguished.
1231 */
1232 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1233 if (res && ops->regs_valid) {
1234 int i = 0;
1235
1236 while (ops->regs[i]) {
1237 if (ops->regs[i] == res->start) {
1238 bsp_priv->id = i;
1239 break;
1240 }
1241 i++;
1242 }
1243 }
1244
1245 bsp_priv->regulator = devm_regulator_get(dev, "phy");
1246 if (IS_ERR(bsp_priv->regulator)) {
1247 ret = PTR_ERR(bsp_priv->regulator);
1248 dev_err_probe(dev, ret, "failed to get phy regulator\n");
1249 return ERR_PTR(ret);
1250 }
1251
1252 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
1253 if (ret) {
1254 dev_err(dev, "Can not read property: clock_in_out.\n");
1255 bsp_priv->clock_input = true;
1256 } else {
1257 dev_info(dev, "clock input or output? (%s).\n",
1258 strings);
1259 if (!strcmp(strings, "input"))
1260 bsp_priv->clock_input = true;
1261 else
1262 bsp_priv->clock_input = false;
1263 }
1264
1265 ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
1266 if (ret) {
1267 bsp_priv->tx_delay = 0x30;
1268 dev_err(dev, "Can not read property: tx_delay.");
1269 dev_err(dev, "set tx_delay to 0x%x\n",
1270 bsp_priv->tx_delay);
1271 } else {
1272 dev_info(dev, "TX delay(0x%x).\n", value);
1273 bsp_priv->tx_delay = value;
1274 }
1275
1276 ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
1277 if (ret) {
1278 bsp_priv->rx_delay = 0x10;
1279 dev_err(dev, "Can not read property: rx_delay.");
1280 dev_err(dev, "set rx_delay to 0x%x\n",
1281 bsp_priv->rx_delay);
1282 } else {
1283 dev_info(dev, "RX delay(0x%x).\n", value);
1284 bsp_priv->rx_delay = value;
1285 }
1286
1287 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1288 "rockchip,grf");
1289 if (IS_ERR(bsp_priv->grf)) {
1290 dev_err_probe(dev, PTR_ERR(bsp_priv->grf),
1291 "failed to lookup rockchip,grf\n");
1292 return ERR_CAST(bsp_priv->grf);
1293 }
1294
1295 if (ops->php_grf_required) {
1296 bsp_priv->php_grf =
1297 syscon_regmap_lookup_by_phandle(dev->of_node,
1298 "rockchip,php-grf");
1299 if (IS_ERR(bsp_priv->php_grf)) {
1300 dev_err_probe(dev, PTR_ERR(bsp_priv->php_grf),
1301 "failed to lookup rockchip,php-grf\n");
1302 return ERR_CAST(bsp_priv->php_grf);
1303 }
1304 }
1305
1306 if (plat->phy_node) {
1307 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
1308 "phy-is-integrated");
1309 if (bsp_priv->integrated_phy) {
1310 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
1311 if (IS_ERR(bsp_priv->phy_reset)) {
1312 dev_err(&pdev->dev, "No PHY reset control found.\n");
1313 bsp_priv->phy_reset = NULL;
1314 }
1315 }
1316 }
1317 dev_info(dev, "integrated PHY? (%s).\n",
1318 bsp_priv->integrated_phy ? "yes" : "no");
1319
1320 bsp_priv->dev = dev;
1321
1322 /* Set the default phy_intf_sel and RMII mode register parameters. */
1323 bsp_priv->gmac_grf_reg = ops->gmac_grf_reg;
1324 bsp_priv->gmac_phy_intf_sel_mask = ops->gmac_phy_intf_sel_mask;
1325 bsp_priv->gmac_rmii_mode_mask = ops->gmac_rmii_mode_mask;
1326
1327 /* Set the default clock control register related parameters */
1328 bsp_priv->clock_grf_reg = ops->clock_grf_reg;
1329 bsp_priv->clock = ops->clock;
1330
1331 bsp_priv->supports_rgmii = ops->supports_rgmii || !!ops->set_to_rgmii;
1332 bsp_priv->supports_rmii = ops->supports_rmii || !!ops->set_to_rmii;
1333
1334 if (ops->init) {
1335 ret = ops->init(bsp_priv);
1336 if (ret) {
1337 reset_control_put(bsp_priv->phy_reset);
1338 dev_err_probe(dev, ret, "failed to init BSP\n");
1339 return ERR_PTR(ret);
1340 }
1341 }
1342
1343 if (bsp_priv->clock.io_clksel_cru_mask &&
1344 bsp_priv->clock.io_clksel_io_mask)
1345 dev_warn(dev, "both CRU and IO io_clksel masks should not be populated - driver may malfunction\n");
1346
1347 return bsp_priv;
1348 }
1349
rk_gmac_check_ops(struct rk_priv_data * bsp_priv)1350 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv)
1351 {
1352 switch (bsp_priv->phy_iface) {
1353 case PHY_INTERFACE_MODE_RGMII:
1354 case PHY_INTERFACE_MODE_RGMII_ID:
1355 case PHY_INTERFACE_MODE_RGMII_RXID:
1356 case PHY_INTERFACE_MODE_RGMII_TXID:
1357 if (!bsp_priv->supports_rgmii)
1358 return -EINVAL;
1359 break;
1360 case PHY_INTERFACE_MODE_RMII:
1361 if (!bsp_priv->supports_rmii)
1362 return -EINVAL;
1363 break;
1364 default:
1365 dev_err(bsp_priv->dev,
1366 "unsupported interface %d", bsp_priv->phy_iface);
1367 }
1368 return 0;
1369 }
1370
rk_gmac_powerup(struct rk_priv_data * bsp_priv)1371 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
1372 {
1373 struct device *dev = bsp_priv->dev;
1374 u32 val;
1375 int ret;
1376 u8 intf;
1377
1378 ret = rk_gmac_check_ops(bsp_priv);
1379 if (ret)
1380 return ret;
1381
1382 ret = rk_get_phy_intf_sel(bsp_priv->phy_iface);
1383 if (ret < 0)
1384 return ret;
1385
1386 intf = ret;
1387
1388 ret = gmac_clk_enable(bsp_priv, true);
1389 if (ret)
1390 return ret;
1391
1392 if (bsp_priv->gmac_phy_intf_sel_mask ||
1393 bsp_priv->gmac_rmii_mode_mask) {
1394 /* If defined, encode the phy_intf_sel value */
1395 val = rk_encode_wm16(intf, bsp_priv->gmac_phy_intf_sel_mask);
1396
1397 /* If defined, encode the RMII mode mask setting. */
1398 val |= rk_encode_wm16(intf == PHY_INTF_SEL_RMII,
1399 bsp_priv->gmac_rmii_mode_mask);
1400
1401 ret = rk_write_gmac_grf_reg(bsp_priv, val);
1402 if (ret < 0) {
1403 gmac_clk_enable(bsp_priv, false);
1404 return ret;
1405 }
1406 }
1407
1408 if (bsp_priv->clock.rmii_mode_mask) {
1409 val = rk_encode_wm16(intf == PHY_INTF_SEL_RMII,
1410 bsp_priv->clock.rmii_mode_mask);
1411
1412 ret = rk_write_clock_grf_reg(bsp_priv, val);
1413 if (ret < 0) {
1414 gmac_clk_enable(bsp_priv, false);
1415 return ret;
1416 }
1417 }
1418
1419 /*rmii or rgmii*/
1420 switch (bsp_priv->phy_iface) {
1421 case PHY_INTERFACE_MODE_RGMII:
1422 dev_info(dev, "init for RGMII\n");
1423 if (bsp_priv->ops->set_to_rgmii)
1424 bsp_priv->ops->set_to_rgmii(bsp_priv,
1425 bsp_priv->tx_delay,
1426 bsp_priv->rx_delay);
1427 break;
1428 case PHY_INTERFACE_MODE_RGMII_ID:
1429 dev_info(dev, "init for RGMII_ID\n");
1430 if (bsp_priv->ops->set_to_rgmii)
1431 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
1432 break;
1433 case PHY_INTERFACE_MODE_RGMII_RXID:
1434 dev_info(dev, "init for RGMII_RXID\n");
1435 if (bsp_priv->ops->set_to_rgmii)
1436 bsp_priv->ops->set_to_rgmii(bsp_priv,
1437 bsp_priv->tx_delay, 0);
1438 break;
1439 case PHY_INTERFACE_MODE_RGMII_TXID:
1440 dev_info(dev, "init for RGMII_TXID\n");
1441 if (bsp_priv->ops->set_to_rgmii)
1442 bsp_priv->ops->set_to_rgmii(bsp_priv,
1443 0, bsp_priv->rx_delay);
1444 break;
1445 case PHY_INTERFACE_MODE_RMII:
1446 dev_info(dev, "init for RMII\n");
1447 if (bsp_priv->ops->set_to_rmii)
1448 bsp_priv->ops->set_to_rmii(bsp_priv);
1449 break;
1450 default:
1451 dev_err(dev, "NO interface defined!\n");
1452 }
1453
1454 ret = rk_phy_powerup(bsp_priv);
1455 if (ret) {
1456 gmac_clk_enable(bsp_priv, false);
1457 return ret;
1458 }
1459
1460 pm_runtime_get_sync(dev);
1461
1462 if (bsp_priv->integrated_phy && bsp_priv->ops->integrated_phy_powerup)
1463 bsp_priv->ops->integrated_phy_powerup(bsp_priv);
1464
1465 return 0;
1466 }
1467
rk_gmac_powerdown(struct rk_priv_data * gmac)1468 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
1469 {
1470 if (gmac->integrated_phy && gmac->ops->integrated_phy_powerdown)
1471 gmac->ops->integrated_phy_powerdown(gmac);
1472
1473 pm_runtime_put_sync(gmac->dev);
1474
1475 rk_phy_powerdown(gmac);
1476 gmac_clk_enable(gmac, false);
1477 }
1478
rk_get_interfaces(struct stmmac_priv * priv,void * bsp_priv,unsigned long * interfaces)1479 static void rk_get_interfaces(struct stmmac_priv *priv, void *bsp_priv,
1480 unsigned long *interfaces)
1481 {
1482 struct rk_priv_data *rk = bsp_priv;
1483
1484 if (rk->supports_rgmii)
1485 phy_interface_set_rgmii(interfaces);
1486
1487 if (rk->supports_rmii)
1488 __set_bit(PHY_INTERFACE_MODE_RMII, interfaces);
1489 }
1490
rk_set_clk_tx_rate(void * bsp_priv_,struct clk * clk_tx_i,phy_interface_t interface,int speed)1491 static int rk_set_clk_tx_rate(void *bsp_priv_, struct clk *clk_tx_i,
1492 phy_interface_t interface, int speed)
1493 {
1494 struct rk_priv_data *bsp_priv = bsp_priv_;
1495 int ret = -EINVAL;
1496 bool is_100m;
1497 u32 val;
1498
1499 if (bsp_priv->ops->set_speed) {
1500 ret = bsp_priv->ops->set_speed(bsp_priv, interface, speed);
1501 if (ret < 0)
1502 return ret;
1503 }
1504
1505 if (phy_interface_mode_is_rgmii(interface) &&
1506 bsp_priv->clock.gmii_clk_sel_mask) {
1507 ret = rk_gmac_rgmii_clk_div(speed);
1508 if (ret < 0)
1509 return ret;
1510
1511 val = rk_encode_wm16(ret, bsp_priv->clock.gmii_clk_sel_mask);
1512
1513 ret = rk_write_clock_grf_reg(bsp_priv, val);
1514 } else if (interface == PHY_INTERFACE_MODE_RMII &&
1515 (bsp_priv->clock.rmii_clk_sel_mask ||
1516 bsp_priv->clock.mac_speed_mask)) {
1517 is_100m = speed == SPEED_100;
1518 val = rk_encode_wm16(is_100m, bsp_priv->clock.mac_speed_mask) |
1519 rk_encode_wm16(is_100m,
1520 bsp_priv->clock.rmii_clk_sel_mask);
1521
1522 ret = rk_write_clock_grf_reg(bsp_priv, val);
1523 }
1524
1525 return ret;
1526 }
1527
rk_gmac_suspend(struct device * dev,void * bsp_priv_)1528 static int rk_gmac_suspend(struct device *dev, void *bsp_priv_)
1529 {
1530 struct rk_priv_data *bsp_priv = bsp_priv_;
1531
1532 /* Keep the PHY up if we use Wake-on-Lan. */
1533 if (!device_may_wakeup(dev))
1534 rk_gmac_powerdown(bsp_priv);
1535
1536 return 0;
1537 }
1538
rk_gmac_resume(struct device * dev,void * bsp_priv_)1539 static int rk_gmac_resume(struct device *dev, void *bsp_priv_)
1540 {
1541 struct rk_priv_data *bsp_priv = bsp_priv_;
1542
1543 /* The PHY was up for Wake-on-Lan. */
1544 if (!device_may_wakeup(dev))
1545 rk_gmac_powerup(bsp_priv);
1546
1547 return 0;
1548 }
1549
rk_gmac_init(struct device * dev,void * bsp_priv)1550 static int rk_gmac_init(struct device *dev, void *bsp_priv)
1551 {
1552 return rk_gmac_powerup(bsp_priv);
1553 }
1554
rk_gmac_exit(struct device * dev,void * bsp_priv_)1555 static void rk_gmac_exit(struct device *dev, void *bsp_priv_)
1556 {
1557 struct stmmac_priv *priv = netdev_priv(dev_get_drvdata(dev));
1558 struct rk_priv_data *bsp_priv = bsp_priv_;
1559
1560 rk_gmac_powerdown(bsp_priv);
1561
1562 if (priv->plat->phy_node && bsp_priv->integrated_phy)
1563 clk_put(bsp_priv->clk_phy);
1564
1565 reset_control_put(bsp_priv->phy_reset);
1566 }
1567
rk_gmac_probe(struct platform_device * pdev)1568 static int rk_gmac_probe(struct platform_device *pdev)
1569 {
1570 struct plat_stmmacenet_data *plat_dat;
1571 struct stmmac_resources stmmac_res;
1572 const struct rk_gmac_ops *data;
1573 int ret;
1574
1575 data = of_device_get_match_data(&pdev->dev);
1576 if (!data) {
1577 dev_err(&pdev->dev, "no of match data provided\n");
1578 return -EINVAL;
1579 }
1580
1581 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1582 if (ret)
1583 return ret;
1584
1585 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
1586 if (IS_ERR(plat_dat))
1587 return PTR_ERR(plat_dat);
1588
1589 /* If the stmmac is not already selected as gmac4,
1590 * then make sure we fallback to gmac.
1591 */
1592 if (plat_dat->core_type != DWMAC_CORE_GMAC4) {
1593 plat_dat->core_type = DWMAC_CORE_GMAC;
1594 plat_dat->rx_fifo_size = 4096;
1595 plat_dat->tx_fifo_size = 2048;
1596 }
1597
1598 plat_dat->get_interfaces = rk_get_interfaces;
1599 plat_dat->set_clk_tx_rate = rk_set_clk_tx_rate;
1600 plat_dat->init = rk_gmac_init;
1601 plat_dat->exit = rk_gmac_exit;
1602 plat_dat->suspend = rk_gmac_suspend;
1603 plat_dat->resume = rk_gmac_resume;
1604
1605 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
1606 if (IS_ERR(plat_dat->bsp_priv))
1607 return PTR_ERR(plat_dat->bsp_priv);
1608
1609 ret = rk_gmac_clk_init(plat_dat);
1610 if (ret)
1611 return ret;
1612
1613 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
1614 }
1615
1616 static const struct of_device_id rk_gmac_dwmac_match[] = {
1617 { .compatible = "rockchip,px30-gmac", .data = &px30_ops },
1618 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
1619 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
1620 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
1621 { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops },
1622 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
1623 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
1624 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
1625 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
1626 { .compatible = "rockchip,rk3506-gmac", .data = &rk3506_ops },
1627 { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
1628 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
1629 { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },
1630 { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
1631 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
1632 { .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
1633 { }
1634 };
1635 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
1636
1637 static struct platform_driver rk_gmac_dwmac_driver = {
1638 .probe = rk_gmac_probe,
1639 .driver = {
1640 .name = "rk_gmac-dwmac",
1641 .pm = &stmmac_simple_pm_ops,
1642 .of_match_table = rk_gmac_dwmac_match,
1643 },
1644 };
1645 module_platform_driver(rk_gmac_dwmac_driver);
1646
1647 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
1648 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
1649 MODULE_LICENSE("GPL");
1650