1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright Altera Corporation (C) 2014. All rights reserved.
3 *
4 * Adopted from dwmac-sti.c
5 */
6
7 #include <linux/mfd/altera-sysmgr.h>
8 #include <linux/clocksource_ids.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/of_net.h>
12 #include <linux/phy.h>
13 #include <linux/regmap.h>
14 #include <linux/mdio/mdio-regmap.h>
15 #include <linux/pcs-lynx.h>
16 #include <linux/reset.h>
17 #include <linux/stmmac.h>
18
19 #include "dwxgmac2.h"
20 #include "stmmac.h"
21 #include "stmmac_platform.h"
22 #include "stmmac_ptp.h"
23
24 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
25 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
26 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
27 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
28 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
29 #define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010
30 #define SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000100
31
32 #define SYSMGR_FPGAGRP_MODULE_REG 0x00000028
33 #define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004
34 #define SYSMGR_FPGAINTF_EMAC_REG 0x00000070
35 #define SYSMGR_FPGAINTF_EMAC_BIT 0x1
36
37 #define EMAC_SPLITTER_CTRL_REG 0x0
38 #define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3
39 #define EMAC_SPLITTER_CTRL_SPEED_10 0x2
40 #define EMAC_SPLITTER_CTRL_SPEED_100 0x3
41 #define EMAC_SPLITTER_CTRL_SPEED_1000 0x0
42
43 #define SGMII_ADAPTER_CTRL_REG 0x00
44 #define SGMII_ADAPTER_ENABLE 0x0000
45 #define SGMII_ADAPTER_DISABLE 0x0001
46
47 #define SMTG_MDIO_ADDR 0x15
48 #define SMTG_TSC_WORD0 0xC
49 #define SMTG_TSC_WORD1 0xD
50 #define SMTG_TSC_WORD2 0xE
51 #define SMTG_TSC_WORD3 0xF
52 #define SMTG_TSC_SHIFT 16
53
54 struct socfpga_dwmac;
55 struct socfpga_dwmac_ops {
56 int (*set_phy_mode)(struct socfpga_dwmac *dwmac_priv,
57 struct device *dev);
58 void (*setup_plat_dat)(struct socfpga_dwmac *dwmac_priv);
59 };
60
61 struct socfpga_dwmac {
62 u32 reg_offset;
63 u32 reg_shift;
64 struct plat_stmmacenet_data *plat_dat;
65 struct regmap *sys_mgr_base_addr;
66 struct reset_control *stmmac_rst;
67 struct reset_control *stmmac_ocp_rst;
68 void __iomem *splitter_base;
69 void __iomem *tse_pcs_base;
70 void __iomem *sgmii_adapter_base;
71 bool f2h_ptp_ref_clk;
72 const struct socfpga_dwmac_ops *ops;
73 };
74
socfpga_get_plat_phymode(struct socfpga_dwmac * dwmac)75 static phy_interface_t socfpga_get_plat_phymode(struct socfpga_dwmac *dwmac)
76 {
77 return dwmac->plat_dat->phy_interface;
78 }
79
socfpga_sgmii_config(struct socfpga_dwmac * dwmac,bool enable)80 static void socfpga_sgmii_config(struct socfpga_dwmac *dwmac, bool enable)
81 {
82 u16 val = enable ? SGMII_ADAPTER_ENABLE : SGMII_ADAPTER_DISABLE;
83
84 writew(val, dwmac->sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
85 }
86
socfpga_dwmac_fix_mac_speed(void * bsp_priv,phy_interface_t interface,int speed,unsigned int mode)87 static void socfpga_dwmac_fix_mac_speed(void *bsp_priv,
88 phy_interface_t interface, int speed,
89 unsigned int mode)
90 {
91 struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)bsp_priv;
92 void __iomem *sgmii_adapter_base = dwmac->sgmii_adapter_base;
93 phy_interface_t phymode = socfpga_get_plat_phymode(dwmac);
94 void __iomem *splitter_base = dwmac->splitter_base;
95 u32 val;
96
97 if (sgmii_adapter_base)
98 socfpga_sgmii_config(dwmac, false);
99
100 if (splitter_base) {
101 val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
102 val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;
103
104 switch (speed) {
105 case 1000:
106 val |= EMAC_SPLITTER_CTRL_SPEED_1000;
107 break;
108 case 100:
109 val |= EMAC_SPLITTER_CTRL_SPEED_100;
110 break;
111 case 10:
112 val |= EMAC_SPLITTER_CTRL_SPEED_10;
113 break;
114 default:
115 return;
116 }
117 writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
118 }
119
120 if ((phymode == PHY_INTERFACE_MODE_SGMII ||
121 phymode == PHY_INTERFACE_MODE_1000BASEX) && sgmii_adapter_base)
122 socfpga_sgmii_config(dwmac, true);
123 }
124
socfpga_dwmac_parse_data(struct socfpga_dwmac * dwmac,struct device * dev)125 static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
126 {
127 struct device_node *np = dev->of_node;
128 struct regmap *sys_mgr_base_addr;
129 u32 reg_offset, reg_shift;
130 int ret, index;
131 struct device_node *np_splitter = NULL;
132 struct device_node *np_sgmii_adapter = NULL;
133 struct resource res_splitter;
134 struct resource res_tse_pcs;
135 struct resource res_sgmii_adapter;
136
137 sys_mgr_base_addr =
138 altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
139 if (IS_ERR(sys_mgr_base_addr)) {
140 dev_info(dev, "No sysmgr-syscon node found\n");
141 return PTR_ERR(sys_mgr_base_addr);
142 }
143
144 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset);
145 if (ret) {
146 dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
147 return -EINVAL;
148 }
149
150 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift);
151 if (ret) {
152 dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
153 return -EINVAL;
154 }
155
156 dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk");
157
158 np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
159 if (np_splitter) {
160 ret = of_address_to_resource(np_splitter, 0, &res_splitter);
161 of_node_put(np_splitter);
162 if (ret) {
163 dev_info(dev, "Missing emac splitter address\n");
164 return -EINVAL;
165 }
166
167 dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter);
168 if (IS_ERR(dwmac->splitter_base)) {
169 dev_info(dev, "Failed to mapping emac splitter\n");
170 return PTR_ERR(dwmac->splitter_base);
171 }
172 }
173
174 np_sgmii_adapter = of_parse_phandle(np,
175 "altr,gmii-to-sgmii-converter", 0);
176 if (np_sgmii_adapter) {
177 index = of_property_match_string(np_sgmii_adapter, "reg-names",
178 "hps_emac_interface_splitter_avalon_slave");
179
180 if (index >= 0) {
181 if (of_address_to_resource(np_sgmii_adapter, index,
182 &res_splitter)) {
183 dev_err(dev,
184 "%s: ERROR: missing emac splitter address\n",
185 __func__);
186 ret = -EINVAL;
187 goto err_node_put;
188 }
189
190 dwmac->splitter_base =
191 devm_ioremap_resource(dev, &res_splitter);
192
193 if (IS_ERR(dwmac->splitter_base)) {
194 ret = PTR_ERR(dwmac->splitter_base);
195 goto err_node_put;
196 }
197 }
198
199 index = of_property_match_string(np_sgmii_adapter, "reg-names",
200 "gmii_to_sgmii_adapter_avalon_slave");
201
202 if (index >= 0) {
203 if (of_address_to_resource(np_sgmii_adapter, index,
204 &res_sgmii_adapter)) {
205 dev_err(dev,
206 "%s: ERROR: failed mapping adapter\n",
207 __func__);
208 ret = -EINVAL;
209 goto err_node_put;
210 }
211
212 dwmac->sgmii_adapter_base =
213 devm_ioremap_resource(dev, &res_sgmii_adapter);
214
215 if (IS_ERR(dwmac->sgmii_adapter_base)) {
216 ret = PTR_ERR(dwmac->sgmii_adapter_base);
217 goto err_node_put;
218 }
219 }
220
221 index = of_property_match_string(np_sgmii_adapter, "reg-names",
222 "eth_tse_control_port");
223
224 if (index >= 0) {
225 if (of_address_to_resource(np_sgmii_adapter, index,
226 &res_tse_pcs)) {
227 dev_err(dev,
228 "%s: ERROR: failed mapping tse control port\n",
229 __func__);
230 ret = -EINVAL;
231 goto err_node_put;
232 }
233
234 dwmac->tse_pcs_base =
235 devm_ioremap_resource(dev, &res_tse_pcs);
236
237 if (IS_ERR(dwmac->tse_pcs_base)) {
238 ret = PTR_ERR(dwmac->tse_pcs_base);
239 goto err_node_put;
240 }
241 }
242 }
243 dwmac->reg_offset = reg_offset;
244 dwmac->reg_shift = reg_shift;
245 dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
246 of_node_put(np_sgmii_adapter);
247
248 return 0;
249
250 err_node_put:
251 of_node_put(np_sgmii_adapter);
252 return ret;
253 }
254
socfpga_set_phy_mode_common(int phymode,u32 * val)255 static int socfpga_set_phy_mode_common(int phymode, u32 *val)
256 {
257 switch (phymode) {
258 case PHY_INTERFACE_MODE_RGMII:
259 case PHY_INTERFACE_MODE_RGMII_ID:
260 case PHY_INTERFACE_MODE_RGMII_RXID:
261 case PHY_INTERFACE_MODE_RGMII_TXID:
262 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
263 break;
264 case PHY_INTERFACE_MODE_MII:
265 case PHY_INTERFACE_MODE_GMII:
266 case PHY_INTERFACE_MODE_SGMII:
267 case PHY_INTERFACE_MODE_1000BASEX:
268 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
269 break;
270 case PHY_INTERFACE_MODE_RMII:
271 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
272 break;
273 default:
274 return -EINVAL;
275 }
276 return 0;
277 }
278
get_smtgtime(struct mii_bus * mii,int smtg_addr,u64 * smtg_time)279 static void get_smtgtime(struct mii_bus *mii, int smtg_addr, u64 *smtg_time)
280 {
281 u64 ns;
282
283 ns = mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD3);
284 ns <<= SMTG_TSC_SHIFT;
285 ns |= mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD2);
286 ns <<= SMTG_TSC_SHIFT;
287 ns |= mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD1);
288 ns <<= SMTG_TSC_SHIFT;
289 ns |= mdiobus_read(mii, smtg_addr, SMTG_TSC_WORD0);
290
291 *smtg_time = ns;
292 }
293
smtg_crosststamp(ktime_t * device,struct system_counterval_t * system,void * ctx)294 static int smtg_crosststamp(ktime_t *device, struct system_counterval_t *system,
295 void *ctx)
296 {
297 struct stmmac_priv *priv = (struct stmmac_priv *)ctx;
298 u32 num_snapshot, gpio_value, acr_value;
299 void __iomem *ptpaddr = priv->ptpaddr;
300 void __iomem *ioaddr = priv->hw->pcsr;
301 unsigned long flags;
302 u64 smtg_time = 0;
303 u64 ptp_time = 0;
304 int i, ret;
305 u32 v;
306
307 /* Both internal crosstimestamping and external triggered event
308 * timestamping cannot be run concurrently.
309 */
310 if (priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN)
311 return -EBUSY;
312
313 mutex_lock(&priv->aux_ts_lock);
314 /* Enable Internal snapshot trigger */
315 acr_value = readl(ptpaddr + PTP_ACR);
316 acr_value &= ~PTP_ACR_MASK;
317 switch (priv->plat->int_snapshot_num) {
318 case AUX_SNAPSHOT0:
319 acr_value |= PTP_ACR_ATSEN0;
320 break;
321 case AUX_SNAPSHOT1:
322 acr_value |= PTP_ACR_ATSEN1;
323 break;
324 case AUX_SNAPSHOT2:
325 acr_value |= PTP_ACR_ATSEN2;
326 break;
327 case AUX_SNAPSHOT3:
328 acr_value |= PTP_ACR_ATSEN3;
329 break;
330 default:
331 mutex_unlock(&priv->aux_ts_lock);
332 return -EINVAL;
333 }
334 writel(acr_value, ptpaddr + PTP_ACR);
335
336 /* Clear FIFO */
337 acr_value = readl(ptpaddr + PTP_ACR);
338 acr_value |= PTP_ACR_ATSFC;
339 writel(acr_value, ptpaddr + PTP_ACR);
340 /* Release the mutex */
341 mutex_unlock(&priv->aux_ts_lock);
342
343 /* Trigger Internal snapshot signal. Create a rising edge by just toggle
344 * the GPO0 to low and back to high.
345 */
346 gpio_value = readl(ioaddr + XGMAC_GPIO_STATUS);
347 gpio_value &= ~XGMAC_GPIO_GPO0;
348 writel(gpio_value, ioaddr + XGMAC_GPIO_STATUS);
349 gpio_value |= XGMAC_GPIO_GPO0;
350 writel(gpio_value, ioaddr + XGMAC_GPIO_STATUS);
351
352 /* Poll for time sync operation done */
353 ret = readl_poll_timeout(priv->ioaddr + XGMAC_INT_STATUS, v,
354 (v & XGMAC_INT_TSIS), 100, 10000);
355 if (ret) {
356 netdev_err(priv->dev, "%s: Wait for time sync operation timeout\n",
357 __func__);
358 return ret;
359 }
360
361 *system = (struct system_counterval_t) {
362 .cycles = 0,
363 .cs_id = CSID_ARM_ARCH_COUNTER,
364 .use_nsecs = false,
365 };
366
367 num_snapshot = FIELD_GET(XGMAC_TIMESTAMP_ATSNS_MASK,
368 readl(ioaddr + XGMAC_TIMESTAMP_STATUS));
369
370 /* Repeat until the timestamps are from the FIFO last segment */
371 for (i = 0; i < num_snapshot; i++) {
372 read_lock_irqsave(&priv->ptp_lock, flags);
373 stmmac_get_ptptime(priv, ptpaddr, &ptp_time);
374 *device = ns_to_ktime(ptp_time);
375 read_unlock_irqrestore(&priv->ptp_lock, flags);
376 }
377
378 get_smtgtime(priv->mii, SMTG_MDIO_ADDR, &smtg_time);
379 system->cycles = smtg_time;
380
381 return 0;
382 }
383
socfpga_gen5_set_phy_mode(struct socfpga_dwmac * dwmac,struct device * dev)384 static int socfpga_gen5_set_phy_mode(struct socfpga_dwmac *dwmac,
385 struct device *dev)
386 {
387 struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
388 phy_interface_t phymode = socfpga_get_plat_phymode(dwmac);
389 u32 reg_offset = dwmac->reg_offset;
390 u32 reg_shift = dwmac->reg_shift;
391 u32 ctrl, val, module;
392
393 if (socfpga_set_phy_mode_common(phymode, &val)) {
394 dev_err(dev, "bad phy mode %d\n", phymode);
395 return -EINVAL;
396 }
397
398 /* Overwrite val to GMII if splitter core is enabled. The phymode here
399 * is the actual phy mode on phy hardware, but phy interface from
400 * EMAC core is GMII.
401 */
402 if (dwmac->splitter_base)
403 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
404
405 /* Assert reset to the enet controller before changing the phy mode */
406 reset_control_assert(dwmac->stmmac_ocp_rst);
407 reset_control_assert(dwmac->stmmac_rst);
408
409 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
410 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
411 ctrl |= val << reg_shift;
412
413 if (dwmac->f2h_ptp_ref_clk ||
414 phymode == PHY_INTERFACE_MODE_MII ||
415 phymode == PHY_INTERFACE_MODE_GMII ||
416 phymode == PHY_INTERFACE_MODE_SGMII) {
417 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
418 &module);
419 module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));
420 regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
421 module);
422 }
423
424 if (dwmac->f2h_ptp_ref_clk)
425 ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
426 else
427 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK <<
428 (reg_shift / 2));
429
430 regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
431
432 /* Deassert reset for the phy configuration to be sampled by
433 * the enet controller, and operation to start in requested mode
434 */
435 reset_control_deassert(dwmac->stmmac_ocp_rst);
436 reset_control_deassert(dwmac->stmmac_rst);
437 if (phymode == PHY_INTERFACE_MODE_SGMII)
438 socfpga_sgmii_config(dwmac, true);
439
440 return 0;
441 }
442
socfpga_gen10_set_phy_mode(struct socfpga_dwmac * dwmac,struct device * dev)443 static int socfpga_gen10_set_phy_mode(struct socfpga_dwmac *dwmac,
444 struct device *dev)
445 {
446 struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
447 phy_interface_t phymode = socfpga_get_plat_phymode(dwmac);
448 u32 reg_offset = dwmac->reg_offset;
449 u32 reg_shift = dwmac->reg_shift;
450 u32 ctrl, val, module;
451
452 if (socfpga_set_phy_mode_common(phymode, &val))
453 return -EINVAL;
454
455 /* Overwrite val to GMII if splitter core is enabled. The phymode here
456 * is the actual phy mode on phy hardware, but phy interface from
457 * EMAC core is GMII.
458 */
459 if (dwmac->splitter_base)
460 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
461
462 /* Assert reset to the enet controller before changing the phy mode */
463 reset_control_assert(dwmac->stmmac_ocp_rst);
464 reset_control_assert(dwmac->stmmac_rst);
465
466 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
467 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK);
468 ctrl |= val;
469
470 if (dwmac->f2h_ptp_ref_clk ||
471 phymode == PHY_INTERFACE_MODE_MII ||
472 phymode == PHY_INTERFACE_MODE_GMII ||
473 phymode == PHY_INTERFACE_MODE_SGMII) {
474 ctrl |= SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK;
475 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAINTF_EMAC_REG,
476 &module);
477 module |= (SYSMGR_FPGAINTF_EMAC_BIT << reg_shift);
478 regmap_write(sys_mgr_base_addr, SYSMGR_FPGAINTF_EMAC_REG,
479 module);
480 } else {
481 ctrl &= ~SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK;
482 }
483
484 regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
485
486 /* Deassert reset for the phy configuration to be sampled by
487 * the enet controller, and operation to start in requested mode
488 */
489 reset_control_deassert(dwmac->stmmac_ocp_rst);
490 reset_control_deassert(dwmac->stmmac_rst);
491 if (phymode == PHY_INTERFACE_MODE_SGMII)
492 socfpga_sgmii_config(dwmac, true);
493 return 0;
494 }
495
socfpga_dwmac_pcs_init(struct stmmac_priv * priv)496 static int socfpga_dwmac_pcs_init(struct stmmac_priv *priv)
497 {
498 struct socfpga_dwmac *dwmac = priv->plat->bsp_priv;
499 struct regmap_config pcs_regmap_cfg = {
500 .reg_bits = 16,
501 .val_bits = 16,
502 .reg_shift = REGMAP_UPSHIFT(1),
503 };
504 struct mdio_regmap_config mrc;
505 struct regmap *pcs_regmap;
506 struct phylink_pcs *pcs;
507 struct mii_bus *pcs_bus;
508
509 if (!dwmac->tse_pcs_base)
510 return 0;
511
512 pcs_regmap = devm_regmap_init_mmio(priv->device, dwmac->tse_pcs_base,
513 &pcs_regmap_cfg);
514 if (IS_ERR(pcs_regmap))
515 return PTR_ERR(pcs_regmap);
516
517 memset(&mrc, 0, sizeof(mrc));
518 mrc.regmap = pcs_regmap;
519 mrc.parent = priv->device;
520 mrc.valid_addr = 0x0;
521 mrc.autoscan = false;
522
523 /* Can't use ndev->name here because it will not have been initialised,
524 * and in any case, the user can rename network interfaces at runtime.
525 */
526 snprintf(mrc.name, MII_BUS_ID_SIZE, "%s-pcs-mii",
527 dev_name(priv->device));
528 pcs_bus = devm_mdio_regmap_register(priv->device, &mrc);
529 if (IS_ERR(pcs_bus))
530 return PTR_ERR(pcs_bus);
531
532 pcs = lynx_pcs_create_mdiodev(pcs_bus, 0);
533 if (IS_ERR(pcs))
534 return PTR_ERR(pcs);
535
536 priv->hw->phylink_pcs = pcs;
537 return 0;
538 }
539
socfpga_dwmac_pcs_exit(struct stmmac_priv * priv)540 static void socfpga_dwmac_pcs_exit(struct stmmac_priv *priv)
541 {
542 if (priv->hw->phylink_pcs)
543 lynx_pcs_destroy(priv->hw->phylink_pcs);
544 }
545
socfpga_dwmac_select_pcs(struct stmmac_priv * priv,phy_interface_t interface)546 static struct phylink_pcs *socfpga_dwmac_select_pcs(struct stmmac_priv *priv,
547 phy_interface_t interface)
548 {
549 return priv->hw->phylink_pcs;
550 }
551
socfpga_dwmac_init(struct device * dev,void * bsp_priv)552 static int socfpga_dwmac_init(struct device *dev, void *bsp_priv)
553 {
554 struct socfpga_dwmac *dwmac = bsp_priv;
555
556 return dwmac->ops->set_phy_mode(dwmac, dev);
557 }
558
socfpga_gen5_setup_plat_dat(struct socfpga_dwmac * dwmac)559 static void socfpga_gen5_setup_plat_dat(struct socfpga_dwmac *dwmac)
560 {
561 struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
562
563 plat_dat->core_type = DWMAC_CORE_GMAC;
564
565 /* Rx watchdog timer in dwmac is buggy in this hw */
566 plat_dat->riwt_off = true;
567 }
568
socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac * dwmac)569 static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)
570 {
571 struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
572
573 plat_dat->core_type = DWMAC_CORE_XGMAC;
574
575 /* Enable TSO */
576 plat_dat->flags |= STMMAC_FLAG_TSO_EN;
577
578 /* Enable TBS */
579 switch (plat_dat->tx_queues_to_use) {
580 case 8:
581 plat_dat->tx_queues_cfg[7].tbs_en = true;
582 fallthrough;
583 case 7:
584 plat_dat->tx_queues_cfg[6].tbs_en = true;
585 break;
586 default:
587 /* Tx Queues 0 - 5 doesn't support TBS on Agilex5 */
588 break;
589 }
590
591 /* Hw supported cross-timestamp */
592 plat_dat->int_snapshot_num = AUX_SNAPSHOT0;
593 plat_dat->crosststamp = smtg_crosststamp;
594 }
595
socfpga_dwmac_probe(struct platform_device * pdev)596 static int socfpga_dwmac_probe(struct platform_device *pdev)
597 {
598 struct plat_stmmacenet_data *plat_dat;
599 struct stmmac_resources stmmac_res;
600 struct device *dev = &pdev->dev;
601 int ret;
602 struct socfpga_dwmac *dwmac;
603 const struct socfpga_dwmac_ops *ops;
604
605 ops = device_get_match_data(&pdev->dev);
606 if (!ops) {
607 dev_err(&pdev->dev, "no of match data provided\n");
608 return -EINVAL;
609 }
610
611 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
612 if (ret)
613 return ret;
614
615 plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
616 if (IS_ERR(plat_dat))
617 return PTR_ERR(plat_dat);
618
619 dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
620 if (!dwmac)
621 return -ENOMEM;
622
623 dwmac->stmmac_ocp_rst = devm_reset_control_get_optional(dev, "stmmaceth-ocp");
624 if (IS_ERR(dwmac->stmmac_ocp_rst)) {
625 ret = PTR_ERR(dwmac->stmmac_ocp_rst);
626 dev_err(dev, "error getting reset control of ocp %d\n", ret);
627 return ret;
628 }
629
630 reset_control_deassert(dwmac->stmmac_ocp_rst);
631
632 ret = socfpga_dwmac_parse_data(dwmac, dev);
633 if (ret) {
634 dev_err(dev, "Unable to parse OF data\n");
635 return ret;
636 }
637
638 /* The socfpga driver needs to control the stmmac reset to set the phy
639 * mode. Create a copy of the core reset handle so it can be used by
640 * the driver later.
641 */
642 dwmac->stmmac_rst = plat_dat->stmmac_rst;
643 dwmac->ops = ops;
644 dwmac->plat_dat = plat_dat;
645
646 plat_dat->bsp_priv = dwmac;
647 plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
648 plat_dat->init = socfpga_dwmac_init;
649 plat_dat->pcs_init = socfpga_dwmac_pcs_init;
650 plat_dat->pcs_exit = socfpga_dwmac_pcs_exit;
651 plat_dat->select_pcs = socfpga_dwmac_select_pcs;
652
653 ops->setup_plat_dat(dwmac);
654
655 return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
656 }
657
658 static const struct socfpga_dwmac_ops socfpga_gen5_ops = {
659 .set_phy_mode = socfpga_gen5_set_phy_mode,
660 .setup_plat_dat = socfpga_gen5_setup_plat_dat,
661 };
662
663 static const struct socfpga_dwmac_ops socfpga_gen10_ops = {
664 .set_phy_mode = socfpga_gen10_set_phy_mode,
665 .setup_plat_dat = socfpga_gen5_setup_plat_dat,
666 };
667
668 static const struct socfpga_dwmac_ops socfpga_agilex5_ops = {
669 .set_phy_mode = socfpga_gen10_set_phy_mode,
670 .setup_plat_dat = socfpga_agilex5_setup_plat_dat,
671 };
672
673 static const struct of_device_id socfpga_dwmac_match[] = {
674 { .compatible = "altr,socfpga-stmmac", .data = &socfpga_gen5_ops },
675 { .compatible = "altr,socfpga-stmmac-a10-s10", .data = &socfpga_gen10_ops },
676 { .compatible = "altr,socfpga-stmmac-agilex5", .data = &socfpga_agilex5_ops },
677 { }
678 };
679 MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);
680
681 static struct platform_driver socfpga_dwmac_driver = {
682 .probe = socfpga_dwmac_probe,
683 .driver = {
684 .name = "socfpga-dwmac",
685 .pm = &stmmac_pltfr_pm_ops,
686 .of_match_table = socfpga_dwmac_match,
687 },
688 };
689 module_platform_driver(socfpga_dwmac_driver);
690
691 MODULE_DESCRIPTION("Altera SOC DWMAC Specific Glue layer");
692 MODULE_LICENSE("GPL v2");
693