1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Microsemi/Microchip SoCs serial gpio driver
4 *
5 * Author: Lars Povlsen <lars.povlsen@microchip.com>
6 *
7 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/clk.h>
13 #include <linux/gpio/driver.h>
14 #include <linux/io.h>
15 #include <linux/mfd/ocelot.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/property.h>
20 #include <linux/regmap.h>
21 #include <linux/reset.h>
22 #include <linux/spinlock.h>
23
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinmux.h>
26
27 #include "core.h"
28 #include "pinconf.h"
29
30 #define SGPIO_BITS_PER_WORD 32
31 #define SGPIO_MAX_BITS 4
32 #define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */
33
34 enum {
35 REG_INPUT_DATA,
36 REG_PORT_CONFIG,
37 REG_PORT_ENABLE,
38 REG_SIO_CONFIG,
39 REG_SIO_CLOCK,
40 REG_INT_POLARITY,
41 REG_INT_TRIGGER,
42 REG_INT_ACK,
43 REG_INT_ENABLE,
44 REG_INT_IDENT,
45 MAXREG
46 };
47
48 enum {
49 SGPIO_ARCH_LUTON,
50 SGPIO_ARCH_OCELOT,
51 SGPIO_ARCH_SPARX5,
52 };
53
54 enum {
55 SGPIO_FLAGS_HAS_IRQ = BIT(0),
56 };
57
58 struct sgpio_properties {
59 int arch;
60 int flags;
61 u8 regoff[MAXREG];
62 };
63
64 #define SGPIO_LUTON_AUTO_REPEAT BIT(5)
65 #define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2)
66 #define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0)
67 #define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0)
68
69 #define SGPIO_OCELOT_AUTO_REPEAT BIT(10)
70 #define SGPIO_OCELOT_SINGLE_SHOT BIT(11)
71 #define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7)
72 #define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8)
73 #define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12)
74
75 #define SGPIO_SPARX5_AUTO_REPEAT BIT(6)
76 #define SGPIO_SPARX5_SINGLE_SHOT BIT(7)
77 #define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3)
78 #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8)
79 #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12)
80
81 #define SGPIO_MASTER_INTR_ENA BIT(0)
82
83 #define SGPIO_INT_TRG_LEVEL 0
84 #define SGPIO_INT_TRG_EDGE 1
85 #define SGPIO_INT_TRG_EDGE_FALL 2
86 #define SGPIO_INT_TRG_EDGE_RISE 3
87
88 #define SGPIO_TRG_LEVEL_HIGH 0
89 #define SGPIO_TRG_LEVEL_LOW 1
90
91 static const struct sgpio_properties properties_luton = {
92 .arch = SGPIO_ARCH_LUTON,
93 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
94 };
95
96 static const struct sgpio_properties properties_ocelot = {
97 .arch = SGPIO_ARCH_OCELOT,
98 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
99 };
100
101 static const struct sgpio_properties properties_sparx5 = {
102 .arch = SGPIO_ARCH_SPARX5,
103 .flags = SGPIO_FLAGS_HAS_IRQ,
104 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 },
105 };
106
107 static const char * const functions[] = { "gpio" };
108
109 struct sgpio_bank {
110 struct sgpio_priv *priv;
111 bool is_input;
112 struct gpio_chip gpio;
113 struct pinctrl_desc pctl_desc;
114 };
115
116 struct sgpio_priv {
117 struct device *dev;
118 struct sgpio_bank in;
119 struct sgpio_bank out;
120 u32 bitcount;
121 u32 ports;
122 u32 clock;
123 struct regmap *regs;
124 const struct sgpio_properties *properties;
125 spinlock_t lock;
126 /* protects the config register and single shot mode */
127 struct mutex poll_lock;
128 };
129
130 struct sgpio_port_addr {
131 u8 port;
132 u8 bit;
133 };
134
sgpio_pin_to_addr(struct sgpio_priv * priv,int pin,struct sgpio_port_addr * addr)135 static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin,
136 struct sgpio_port_addr *addr)
137 {
138 addr->port = pin / priv->bitcount;
139 addr->bit = pin % priv->bitcount;
140 }
141
sgpio_addr_to_pin(struct sgpio_priv * priv,int port,int bit)142 static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit)
143 {
144 return bit + port * priv->bitcount;
145 }
146
sgpio_get_addr(struct sgpio_priv * priv,u32 rno,u32 off)147 static inline u32 sgpio_get_addr(struct sgpio_priv *priv, u32 rno, u32 off)
148 {
149 return (priv->properties->regoff[rno] + off) *
150 regmap_get_reg_stride(priv->regs);
151 }
152
sgpio_readl(struct sgpio_priv * priv,u32 rno,u32 off)153 static u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off)
154 {
155 u32 addr = sgpio_get_addr(priv, rno, off);
156 u32 val = 0;
157 int ret;
158
159 ret = regmap_read(priv->regs, addr, &val);
160 WARN_ONCE(ret, "error reading sgpio reg %d\n", ret);
161
162 return val;
163 }
164
sgpio_writel(struct sgpio_priv * priv,u32 val,u32 rno,u32 off)165 static void sgpio_writel(struct sgpio_priv *priv,
166 u32 val, u32 rno, u32 off)
167 {
168 u32 addr = sgpio_get_addr(priv, rno, off);
169 int ret;
170
171 ret = regmap_write(priv->regs, addr, val);
172 WARN_ONCE(ret, "error writing sgpio reg %d\n", ret);
173 }
174
sgpio_clrsetbits(struct sgpio_priv * priv,u32 rno,u32 off,u32 clear,u32 set)175 static inline void sgpio_clrsetbits(struct sgpio_priv *priv,
176 u32 rno, u32 off, u32 clear, u32 set)
177 {
178 u32 addr = sgpio_get_addr(priv, rno, off);
179 int ret;
180
181 ret = regmap_update_bits(priv->regs, addr, clear | set, set);
182 WARN_ONCE(ret, "error updating sgpio reg %d\n", ret);
183 }
184
sgpio_configure_bitstream(struct sgpio_priv * priv)185 static inline void sgpio_configure_bitstream(struct sgpio_priv *priv)
186 {
187 int width = priv->bitcount - 1;
188 u32 clr, set;
189
190 switch (priv->properties->arch) {
191 case SGPIO_ARCH_LUTON:
192 clr = SGPIO_LUTON_PORT_WIDTH;
193 set = SGPIO_LUTON_AUTO_REPEAT |
194 FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width);
195 break;
196 case SGPIO_ARCH_OCELOT:
197 clr = SGPIO_OCELOT_PORT_WIDTH;
198 set = SGPIO_OCELOT_AUTO_REPEAT |
199 FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width);
200 break;
201 case SGPIO_ARCH_SPARX5:
202 clr = SGPIO_SPARX5_PORT_WIDTH;
203 set = SGPIO_SPARX5_AUTO_REPEAT |
204 FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width);
205 break;
206 default:
207 return;
208 }
209 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set);
210 }
211
sgpio_configure_clock(struct sgpio_priv * priv,u32 clkfrq)212 static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq)
213 {
214 u32 clr, set;
215
216 switch (priv->properties->arch) {
217 case SGPIO_ARCH_LUTON:
218 clr = SGPIO_LUTON_CLK_FREQ;
219 set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq);
220 break;
221 case SGPIO_ARCH_OCELOT:
222 clr = SGPIO_OCELOT_CLK_FREQ;
223 set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq);
224 break;
225 case SGPIO_ARCH_SPARX5:
226 clr = SGPIO_SPARX5_CLK_FREQ;
227 set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq);
228 break;
229 default:
230 return;
231 }
232 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set);
233 }
234
sgpio_single_shot(struct sgpio_priv * priv)235 static int sgpio_single_shot(struct sgpio_priv *priv)
236 {
237 u32 addr = sgpio_get_addr(priv, REG_SIO_CONFIG, 0);
238 int ret, ret2;
239 u32 ctrl;
240 unsigned int single_shot;
241 unsigned int auto_repeat;
242
243 switch (priv->properties->arch) {
244 case SGPIO_ARCH_LUTON:
245 /* not supported for now */
246 return 0;
247 case SGPIO_ARCH_OCELOT:
248 single_shot = SGPIO_OCELOT_SINGLE_SHOT;
249 auto_repeat = SGPIO_OCELOT_AUTO_REPEAT;
250 break;
251 case SGPIO_ARCH_SPARX5:
252 single_shot = SGPIO_SPARX5_SINGLE_SHOT;
253 auto_repeat = SGPIO_SPARX5_AUTO_REPEAT;
254 break;
255 default:
256 return -EINVAL;
257 }
258
259 /*
260 * Trigger immediate burst. This only works when auto repeat is turned
261 * off. Otherwise, the single shot bit will never be cleared by the
262 * hardware. Measurements showed that an update might take as long as
263 * the burst gap. On a LAN9668 this is about 50ms for the largest
264 * setting.
265 * After the manual burst, reenable the auto repeat mode again.
266 */
267 guard(mutex)(&priv->poll_lock);
268 ret = regmap_update_bits(priv->regs, addr, single_shot | auto_repeat,
269 single_shot);
270 if (ret)
271 return ret;
272
273 ret = regmap_read_poll_timeout(priv->regs, addr, ctrl,
274 !(ctrl & single_shot), 100, 60000);
275
276 /* reenable auto repeat mode even if there was an error */
277 ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat);
278
279 return ret ?: ret2;
280 }
281
sgpio_output_set(struct sgpio_priv * priv,struct sgpio_port_addr * addr,int value)282 static int sgpio_output_set(struct sgpio_priv *priv,
283 struct sgpio_port_addr *addr,
284 int value)
285 {
286 unsigned int bit = SGPIO_SRC_BITS * addr->bit;
287 u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port);
288 bool changed;
289 u32 clr, set;
290 int ret;
291
292 switch (priv->properties->arch) {
293 case SGPIO_ARCH_LUTON:
294 clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit));
295 set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit);
296 break;
297 case SGPIO_ARCH_OCELOT:
298 clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit));
299 set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit);
300 break;
301 case SGPIO_ARCH_SPARX5:
302 clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit));
303 set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit);
304 break;
305 default:
306 return -EINVAL;
307 }
308
309 ret = regmap_update_bits_check(priv->regs, reg, clr | set, set,
310 &changed);
311 if (ret)
312 return ret;
313
314 if (changed) {
315 ret = sgpio_single_shot(priv);
316 if (ret)
317 return ret;
318 }
319
320 return 0;
321 }
322
sgpio_output_get(struct sgpio_priv * priv,struct sgpio_port_addr * addr)323 static int sgpio_output_get(struct sgpio_priv *priv,
324 struct sgpio_port_addr *addr)
325 {
326 u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port);
327 unsigned int bit = SGPIO_SRC_BITS * addr->bit;
328
329 switch (priv->properties->arch) {
330 case SGPIO_ARCH_LUTON:
331 val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval);
332 break;
333 case SGPIO_ARCH_OCELOT:
334 val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval);
335 break;
336 case SGPIO_ARCH_SPARX5:
337 val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval);
338 break;
339 default:
340 val = 0;
341 break;
342 }
343 return !!(val & BIT(bit));
344 }
345
sgpio_input_get(struct sgpio_priv * priv,struct sgpio_port_addr * addr)346 static int sgpio_input_get(struct sgpio_priv *priv,
347 struct sgpio_port_addr *addr)
348 {
349 return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port));
350 }
351
sgpio_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)352 static int sgpio_pinconf_get(struct pinctrl_dev *pctldev,
353 unsigned int pin, unsigned long *config)
354 {
355 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
356 u32 param = pinconf_to_config_param(*config);
357 struct sgpio_priv *priv = bank->priv;
358 struct sgpio_port_addr addr;
359 int val;
360
361 sgpio_pin_to_addr(priv, pin, &addr);
362
363 switch (param) {
364 case PIN_CONFIG_INPUT_ENABLE:
365 val = bank->is_input;
366 break;
367
368 case PIN_CONFIG_OUTPUT_ENABLE:
369 val = !bank->is_input;
370 break;
371
372 case PIN_CONFIG_LEVEL:
373 if (bank->is_input)
374 return -EINVAL;
375 val = sgpio_output_get(priv, &addr);
376 break;
377
378 default:
379 return -ENOTSUPP;
380 }
381
382 *config = pinconf_to_config_packed(param, val);
383
384 return 0;
385 }
386
sgpio_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)387 static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
388 unsigned long *configs, unsigned int num_configs)
389 {
390 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
391 struct sgpio_priv *priv = bank->priv;
392 struct sgpio_port_addr addr;
393 int cfg, err = 0;
394 u32 param, arg;
395
396 sgpio_pin_to_addr(priv, pin, &addr);
397
398 for (cfg = 0; cfg < num_configs; cfg++) {
399 param = pinconf_to_config_param(configs[cfg]);
400 arg = pinconf_to_config_argument(configs[cfg]);
401
402 switch (param) {
403 case PIN_CONFIG_LEVEL:
404 if (bank->is_input)
405 return -EINVAL;
406 err = sgpio_output_set(priv, &addr, arg);
407 break;
408
409 default:
410 err = -ENOTSUPP;
411 }
412 }
413
414 return err;
415 }
416
417 static const struct pinconf_ops sgpio_confops = {
418 .is_generic = true,
419 .pin_config_get = sgpio_pinconf_get,
420 .pin_config_set = sgpio_pinconf_set,
421 .pin_config_config_dbg_show = pinconf_generic_dump_config,
422 };
423
sgpio_get_functions_count(struct pinctrl_dev * pctldev)424 static int sgpio_get_functions_count(struct pinctrl_dev *pctldev)
425 {
426 return 1;
427 }
428
sgpio_get_function_name(struct pinctrl_dev * pctldev,unsigned int function)429 static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev,
430 unsigned int function)
431 {
432 return functions[0];
433 }
434
sgpio_get_function_groups(struct pinctrl_dev * pctldev,unsigned int function,const char * const ** groups,unsigned * const num_groups)435 static int sgpio_get_function_groups(struct pinctrl_dev *pctldev,
436 unsigned int function,
437 const char *const **groups,
438 unsigned *const num_groups)
439 {
440 *groups = functions;
441 *num_groups = ARRAY_SIZE(functions);
442
443 return 0;
444 }
445
sgpio_pinmux_set_mux(struct pinctrl_dev * pctldev,unsigned int selector,unsigned int group)446 static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev,
447 unsigned int selector, unsigned int group)
448 {
449 return 0;
450 }
451
sgpio_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int pin,bool input)452 static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev,
453 struct pinctrl_gpio_range *range,
454 unsigned int pin, bool input)
455 {
456 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
457
458 return (input == bank->is_input) ? 0 : -EINVAL;
459 }
460
sgpio_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)461 static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev,
462 struct pinctrl_gpio_range *range,
463 unsigned int offset)
464 {
465 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
466 struct sgpio_priv *priv = bank->priv;
467 struct sgpio_port_addr addr;
468
469 sgpio_pin_to_addr(priv, offset, &addr);
470
471 if ((priv->ports & BIT(addr.port)) == 0) {
472 dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n",
473 addr.port, addr.bit);
474 return -EINVAL;
475 }
476
477 return 0;
478 }
479
480 static const struct pinmux_ops sgpio_pmx_ops = {
481 .get_functions_count = sgpio_get_functions_count,
482 .get_function_name = sgpio_get_function_name,
483 .get_function_groups = sgpio_get_function_groups,
484 .set_mux = sgpio_pinmux_set_mux,
485 .gpio_set_direction = sgpio_gpio_set_direction,
486 .gpio_request_enable = sgpio_gpio_request_enable,
487 };
488
sgpio_pctl_get_groups_count(struct pinctrl_dev * pctldev)489 static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev)
490 {
491 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
492
493 return bank->pctl_desc.npins;
494 }
495
sgpio_pctl_get_group_name(struct pinctrl_dev * pctldev,unsigned int group)496 static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev,
497 unsigned int group)
498 {
499 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
500
501 return bank->pctl_desc.pins[group].name;
502 }
503
sgpio_pctl_get_group_pins(struct pinctrl_dev * pctldev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)504 static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev,
505 unsigned int group,
506 const unsigned int **pins,
507 unsigned int *num_pins)
508 {
509 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
510
511 *pins = &bank->pctl_desc.pins[group].number;
512 *num_pins = 1;
513
514 return 0;
515 }
516
517 static const struct pinctrl_ops sgpio_pctl_ops = {
518 .get_groups_count = sgpio_pctl_get_groups_count,
519 .get_group_name = sgpio_pctl_get_group_name,
520 .get_group_pins = sgpio_pctl_get_group_pins,
521 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
522 .dt_free_map = pinconf_generic_dt_free_map,
523 };
524
microchip_sgpio_direction_input(struct gpio_chip * gc,unsigned int gpio)525 static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio)
526 {
527 struct sgpio_bank *bank = gpiochip_get_data(gc);
528
529 /* Fixed-position function */
530 return bank->is_input ? 0 : -EINVAL;
531 }
532
microchip_sgpio_direction_output(struct gpio_chip * gc,unsigned int gpio,int value)533 static int microchip_sgpio_direction_output(struct gpio_chip *gc,
534 unsigned int gpio, int value)
535 {
536 struct sgpio_bank *bank = gpiochip_get_data(gc);
537 struct sgpio_priv *priv = bank->priv;
538 struct sgpio_port_addr addr;
539
540 /* Fixed-position function */
541 if (bank->is_input)
542 return -EINVAL;
543
544 sgpio_pin_to_addr(priv, gpio, &addr);
545
546 return sgpio_output_set(priv, &addr, value);
547 }
548
microchip_sgpio_get_direction(struct gpio_chip * gc,unsigned int gpio)549 static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
550 {
551 struct sgpio_bank *bank = gpiochip_get_data(gc);
552
553 return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
554 }
555
microchip_sgpio_set_value(struct gpio_chip * gc,unsigned int gpio,int value)556 static int microchip_sgpio_set_value(struct gpio_chip *gc, unsigned int gpio,
557 int value)
558 {
559 return microchip_sgpio_direction_output(gc, gpio, value);
560 }
561
microchip_sgpio_get_value(struct gpio_chip * gc,unsigned int gpio)562 static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio)
563 {
564 struct sgpio_bank *bank = gpiochip_get_data(gc);
565 struct sgpio_priv *priv = bank->priv;
566 struct sgpio_port_addr addr;
567
568 sgpio_pin_to_addr(priv, gpio, &addr);
569
570 return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr);
571 }
572
microchip_sgpio_of_xlate(struct gpio_chip * gc,const struct of_phandle_args * gpiospec,u32 * flags)573 static int microchip_sgpio_of_xlate(struct gpio_chip *gc,
574 const struct of_phandle_args *gpiospec,
575 u32 *flags)
576 {
577 struct sgpio_bank *bank = gpiochip_get_data(gc);
578 struct sgpio_priv *priv = bank->priv;
579 int pin;
580
581 /*
582 * Note that the SGIO pin is defined by *2* numbers, a port
583 * number between 0 and 31, and a bit index, 0 to 3.
584 */
585 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD ||
586 gpiospec->args[1] > priv->bitcount)
587 return -EINVAL;
588
589 pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]);
590
591 if (pin > gc->ngpio)
592 return -EINVAL;
593
594 if (flags)
595 *flags = gpiospec->args[2];
596
597 return pin;
598 }
599
microchip_sgpio_get_ports(struct sgpio_priv * priv)600 static int microchip_sgpio_get_ports(struct sgpio_priv *priv)
601 {
602 const char *range_property_name = "microchip,sgpio-port-ranges";
603 struct device *dev = priv->dev;
604 u32 range_params[64];
605 int i, nranges, ret;
606
607 /* Calculate port mask */
608 nranges = device_property_count_u32(dev, range_property_name);
609 if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) {
610 dev_err(dev, "%s port range: '%s' property\n",
611 nranges == -EINVAL ? "Missing" : "Invalid",
612 range_property_name);
613 return -EINVAL;
614 }
615
616 ret = device_property_read_u32_array(dev, range_property_name,
617 range_params, nranges);
618 if (ret) {
619 dev_err(dev, "failed to parse '%s' property: %d\n",
620 range_property_name, ret);
621 return ret;
622 }
623 for (i = 0; i < nranges; i += 2) {
624 int start, end;
625
626 start = range_params[i];
627 end = range_params[i + 1];
628 if (start > end || end >= SGPIO_BITS_PER_WORD) {
629 dev_err(dev, "Ill-formed port-range [%d:%d]\n",
630 start, end);
631 }
632 priv->ports |= GENMASK(end, start);
633 }
634
635 return 0;
636 }
637
microchip_sgpio_irq_settype(struct irq_data * data,int type,int polarity)638 static void microchip_sgpio_irq_settype(struct irq_data *data,
639 int type,
640 int polarity)
641 {
642 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
643 struct sgpio_bank *bank = gpiochip_get_data(chip);
644 unsigned int gpio = irqd_to_hwirq(data);
645 struct sgpio_port_addr addr;
646 unsigned long flags;
647 u32 ena;
648
649 sgpio_pin_to_addr(bank->priv, gpio, &addr);
650
651 spin_lock_irqsave(&bank->priv->lock, flags);
652
653 /* Disable interrupt while changing type */
654 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);
655 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);
656
657 /* Type value spread over 2 registers sets: low, high bit */
658 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit,
659 BIT(addr.port), (!!(type & 0x1)) << addr.port);
660 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit,
661 BIT(addr.port), (!!(type & 0x2)) << addr.port);
662
663 if (type == SGPIO_INT_TRG_LEVEL)
664 sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit,
665 BIT(addr.port), polarity << addr.port);
666
667 /* Possibly re-enable interrupts */
668 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);
669
670 spin_unlock_irqrestore(&bank->priv->lock, flags);
671 }
672
microchip_sgpio_irq_setreg(struct irq_data * data,int reg,bool clear)673 static void microchip_sgpio_irq_setreg(struct irq_data *data,
674 int reg,
675 bool clear)
676 {
677 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
678 struct sgpio_bank *bank = gpiochip_get_data(chip);
679 unsigned int gpio = irqd_to_hwirq(data);
680 struct sgpio_port_addr addr;
681
682 sgpio_pin_to_addr(bank->priv, gpio, &addr);
683
684 if (clear)
685 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0);
686 else
687 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port));
688 }
689
microchip_sgpio_irq_mask(struct irq_data * data)690 static void microchip_sgpio_irq_mask(struct irq_data *data)
691 {
692 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
693
694 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true);
695 gpiochip_disable_irq(chip, data->hwirq);
696 }
697
microchip_sgpio_irq_unmask(struct irq_data * data)698 static void microchip_sgpio_irq_unmask(struct irq_data *data)
699 {
700 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
701
702 gpiochip_enable_irq(chip, data->hwirq);
703 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false);
704 }
705
microchip_sgpio_irq_ack(struct irq_data * data)706 static void microchip_sgpio_irq_ack(struct irq_data *data)
707 {
708 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
709 struct sgpio_bank *bank = gpiochip_get_data(chip);
710 unsigned int gpio = irqd_to_hwirq(data);
711 struct sgpio_port_addr addr;
712
713 sgpio_pin_to_addr(bank->priv, gpio, &addr);
714
715 sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit);
716 }
717
microchip_sgpio_irq_set_type(struct irq_data * data,unsigned int type)718 static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type)
719 {
720 switch (type) {
721 case IRQ_TYPE_EDGE_BOTH:
722 irq_set_handler_locked(data, handle_edge_irq);
723 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0);
724 break;
725 case IRQ_TYPE_EDGE_RISING:
726 irq_set_handler_locked(data, handle_edge_irq);
727 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0);
728 break;
729 case IRQ_TYPE_EDGE_FALLING:
730 irq_set_handler_locked(data, handle_edge_irq);
731 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0);
732 break;
733 case IRQ_TYPE_LEVEL_HIGH:
734 irq_set_handler_locked(data, handle_level_irq);
735 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH);
736 break;
737 case IRQ_TYPE_LEVEL_LOW:
738 irq_set_handler_locked(data, handle_level_irq);
739 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW);
740 break;
741 default:
742 return -EINVAL;
743 }
744
745 return 0;
746 }
747
748 static const struct irq_chip microchip_sgpio_irqchip = {
749 .name = "gpio",
750 .irq_mask = microchip_sgpio_irq_mask,
751 .irq_ack = microchip_sgpio_irq_ack,
752 .irq_unmask = microchip_sgpio_irq_unmask,
753 .irq_set_type = microchip_sgpio_irq_set_type,
754 .flags = IRQCHIP_IMMUTABLE,
755 GPIOCHIP_IRQ_RESOURCE_HELPERS,
756 };
757
sgpio_irq_handler(struct irq_desc * desc)758 static void sgpio_irq_handler(struct irq_desc *desc)
759 {
760 struct irq_chip *parent_chip = irq_desc_get_chip(desc);
761 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
762 struct sgpio_bank *bank = gpiochip_get_data(chip);
763 struct sgpio_priv *priv = bank->priv;
764 int bit, port, gpio;
765 long val;
766
767 for (bit = 0; bit < priv->bitcount; bit++) {
768 val = sgpio_readl(priv, REG_INT_IDENT, bit);
769 if (!val)
770 continue;
771
772 chained_irq_enter(parent_chip, desc);
773
774 for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) {
775 gpio = sgpio_addr_to_pin(priv, port, bit);
776 generic_handle_domain_irq(chip->irq.domain, gpio);
777 }
778
779 chained_irq_exit(parent_chip, desc);
780 }
781 }
782
microchip_sgpio_register_bank(struct device * dev,struct sgpio_priv * priv,struct fwnode_handle * fwnode,int bankno)783 static int microchip_sgpio_register_bank(struct device *dev,
784 struct sgpio_priv *priv,
785 struct fwnode_handle *fwnode,
786 int bankno)
787 {
788 struct pinctrl_pin_desc *pins;
789 struct pinctrl_desc *pctl_desc;
790 struct pinctrl_dev *pctldev;
791 struct sgpio_bank *bank;
792 struct gpio_chip *gc;
793 u32 ngpios;
794 int i, ret;
795
796 /* Get overall bank struct */
797 bank = (bankno == 0) ? &priv->in : &priv->out;
798 bank->priv = priv;
799
800 if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) {
801 dev_info(dev, "failed to get number of gpios for bank%d\n",
802 bankno);
803 ngpios = 64;
804 }
805
806 priv->bitcount = ngpios / SGPIO_BITS_PER_WORD;
807 if (priv->bitcount > SGPIO_MAX_BITS) {
808 dev_err(dev, "Bit width exceeds maximum (%d)\n",
809 SGPIO_MAX_BITS);
810 return -EINVAL;
811 }
812
813 pctl_desc = &bank->pctl_desc;
814 pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput",
815 dev_name(dev),
816 bank->is_input ? "in" : "out");
817 if (!pctl_desc->name)
818 return -ENOMEM;
819
820 pctl_desc->pctlops = &sgpio_pctl_ops;
821 pctl_desc->pmxops = &sgpio_pmx_ops;
822 pctl_desc->confops = &sgpio_confops;
823 pctl_desc->owner = THIS_MODULE;
824
825 pins = devm_kcalloc(dev, ngpios, sizeof(*pins), GFP_KERNEL);
826 if (!pins)
827 return -ENOMEM;
828
829 pctl_desc->npins = ngpios;
830 pctl_desc->pins = pins;
831
832 for (i = 0; i < ngpios; i++) {
833 struct sgpio_port_addr addr;
834
835 sgpio_pin_to_addr(priv, i, &addr);
836
837 pins[i].number = i;
838 pins[i].name = devm_kasprintf(dev, GFP_KERNEL,
839 "SGPIO_%c_p%db%d",
840 bank->is_input ? 'I' : 'O',
841 addr.port, addr.bit);
842 if (!pins[i].name)
843 return -ENOMEM;
844 }
845
846 pctldev = devm_pinctrl_register(dev, pctl_desc, bank);
847 if (IS_ERR(pctldev))
848 return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n");
849
850 gc = &bank->gpio;
851 gc->label = pctl_desc->name;
852 gc->parent = dev;
853 gc->fwnode = fwnode;
854 gc->owner = THIS_MODULE;
855 gc->get_direction = microchip_sgpio_get_direction;
856 gc->direction_input = microchip_sgpio_direction_input;
857 gc->direction_output = microchip_sgpio_direction_output;
858 gc->get = microchip_sgpio_get_value;
859 gc->set = microchip_sgpio_set_value;
860 gc->request = gpiochip_generic_request;
861 gc->free = gpiochip_generic_free;
862 gc->of_xlate = microchip_sgpio_of_xlate;
863 gc->of_gpio_n_cells = 3;
864 gc->base = -1;
865 gc->ngpio = ngpios;
866 gc->can_sleep = !bank->is_input;
867
868 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {
869 int irq;
870
871 irq = fwnode_irq_get(fwnode, 0);
872 if (irq > 0) {
873 struct gpio_irq_chip *girq = &gc->irq;
874
875 gpio_irq_chip_set_chip(girq, µchip_sgpio_irqchip);
876 girq->parent_handler = sgpio_irq_handler;
877 girq->num_parents = 1;
878 girq->parents = devm_kcalloc(dev, 1,
879 sizeof(*girq->parents),
880 GFP_KERNEL);
881 if (!girq->parents)
882 return -ENOMEM;
883 girq->parents[0] = irq;
884 girq->default_type = IRQ_TYPE_NONE;
885 girq->handler = handle_bad_irq;
886
887 /* Disable all individual pins */
888 for (i = 0; i < SGPIO_MAX_BITS; i++)
889 sgpio_writel(priv, 0, REG_INT_ENABLE, i);
890 /* Master enable */
891 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA);
892 }
893 }
894
895 ret = devm_gpiochip_add_data(dev, gc, bank);
896 if (ret)
897 dev_err(dev, "Failed to register: ret %d\n", ret);
898
899 return ret;
900 }
901
microchip_sgpio_probe(struct platform_device * pdev)902 static int microchip_sgpio_probe(struct platform_device *pdev)
903 {
904 int div_clock = 0, ret, port, i, nbanks;
905 struct device *dev = &pdev->dev;
906 struct fwnode_handle *fwnode;
907 struct reset_control *reset;
908 struct sgpio_priv *priv;
909 struct clk *clk;
910 u32 val;
911 struct regmap_config regmap_config = {
912 .reg_bits = 32,
913 .val_bits = 32,
914 .reg_stride = 4,
915 };
916
917 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
918 if (!priv)
919 return -ENOMEM;
920
921 priv->dev = dev;
922 spin_lock_init(&priv->lock);
923 mutex_init(&priv->poll_lock);
924
925 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
926 if (IS_ERR(reset))
927 return dev_err_probe(dev, PTR_ERR(reset), "Failed to get reset\n");
928 reset_control_reset(reset);
929
930 clk = devm_clk_get(dev, NULL);
931 if (IS_ERR(clk))
932 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n");
933
934 div_clock = clk_get_rate(clk);
935 if (device_property_read_u32(dev, "bus-frequency", &priv->clock))
936 priv->clock = 12500000;
937 if (priv->clock == 0 || priv->clock > (div_clock / 2)) {
938 dev_err(dev, "Invalid frequency %d\n", priv->clock);
939 return -EINVAL;
940 }
941
942 priv->regs = ocelot_regmap_from_resource(pdev, 0, ®map_config);
943 if (IS_ERR(priv->regs))
944 return PTR_ERR(priv->regs);
945
946 priv->properties = device_get_match_data(dev);
947 priv->in.is_input = true;
948
949 /* Get rest of device properties */
950 ret = microchip_sgpio_get_ports(priv);
951 if (ret)
952 return ret;
953
954 nbanks = device_get_child_node_count(dev);
955 if (nbanks != 2) {
956 dev_err(dev, "Must have 2 banks (have %d)\n", nbanks);
957 return -EINVAL;
958 }
959
960 i = 0;
961 device_for_each_child_node(dev, fwnode) {
962 ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++);
963 if (ret) {
964 fwnode_handle_put(fwnode);
965 return ret;
966 }
967 }
968
969 if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) {
970 dev_err(dev, "Banks must have same GPIO count\n");
971 return -ERANGE;
972 }
973
974 sgpio_configure_bitstream(priv);
975
976 val = max(2U, div_clock / priv->clock);
977 sgpio_configure_clock(priv, val);
978
979 for (port = 0; port < SGPIO_BITS_PER_WORD; port++)
980 sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
981 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
982
983 return 0;
984 }
985
986 static const struct of_device_id microchip_sgpio_gpio_of_match[] = {
987 {
988 .compatible = "microchip,sparx5-sgpio",
989 .data = &properties_sparx5,
990 }, {
991 .compatible = "mscc,luton-sgpio",
992 .data = &properties_luton,
993 }, {
994 .compatible = "mscc,ocelot-sgpio",
995 .data = &properties_ocelot,
996 }, {
997 /* sentinel */
998 }
999 };
1000 MODULE_DEVICE_TABLE(of, microchip_sgpio_gpio_of_match);
1001
1002 static struct platform_driver microchip_sgpio_pinctrl_driver = {
1003 .driver = {
1004 .name = "pinctrl-microchip-sgpio",
1005 .of_match_table = microchip_sgpio_gpio_of_match,
1006 .suppress_bind_attrs = true,
1007 },
1008 .probe = microchip_sgpio_probe,
1009 };
1010 module_platform_driver(microchip_sgpio_pinctrl_driver);
1011
1012 MODULE_DESCRIPTION("Microchip SGPIO Pinctrl Driver");
1013 MODULE_LICENSE("GPL");
1014