1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ASPEED FMC/SPI Memory Controller Driver
4 *
5 * Copyright (c) 2015-2022, IBM Corporation.
6 * Copyright (c) 2020, ASPEED Corporation.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_platform.h>
14 #include <linux/platform_device.h>
15 #include <linux/spi/spi.h>
16 #include <linux/spi/spi-mem.h>
17
18 #define DEVICE_NAME "spi-aspeed-smc"
19
20 /* Type setting Register */
21 #define CONFIG_REG 0x0
22 #define CONFIG_TYPE_SPI 0x2
23
24 /* CE Control Register */
25 #define CE_CTRL_REG 0x4
26
27 /* CEx Control Register */
28 #define CE0_CTRL_REG 0x10
29 #define CTRL_IO_MODE_MASK GENMASK(30, 28)
30 #define CTRL_IO_SINGLE_DATA 0x0
31 #define CTRL_IO_DUAL_DATA BIT(29)
32 #define CTRL_IO_QUAD_DATA BIT(30)
33 #define CTRL_COMMAND_SHIFT 16
34 #define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
35 #define CTRL_IO_DUMMY_SET(dummy) \
36 (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
37 #define CTRL_FREQ_SEL_SHIFT 8
38 #define CTRL_FREQ_SEL_MASK GENMASK(11, CTRL_FREQ_SEL_SHIFT)
39 #define CTRL_CE_STOP_ACTIVE BIT(2)
40 #define CTRL_IO_MODE_CMD_MASK GENMASK(1, 0)
41 #define CTRL_IO_MODE_NORMAL 0x0
42 #define CTRL_IO_MODE_READ 0x1
43 #define CTRL_IO_MODE_WRITE 0x2
44 #define CTRL_IO_MODE_USER 0x3
45
46 #define CTRL_IO_CMD_MASK 0xf0ff40c3
47
48 /* CEx Address Decoding Range Register */
49 #define CE0_SEGMENT_ADDR_REG 0x30
50
51 #define FULL_DUPLEX_RX_DATA 0x1e4
52
53 /* CEx Read timing compensation register */
54 #define CE0_TIMING_COMPENSATION_REG 0x94
55
56 enum aspeed_spi_ctl_reg_value {
57 ASPEED_SPI_BASE,
58 ASPEED_SPI_READ,
59 ASPEED_SPI_WRITE,
60 ASPEED_SPI_MAX,
61 };
62
63 struct aspeed_spi;
64
65 struct aspeed_spi_chip {
66 struct aspeed_spi *aspi;
67 u32 cs;
68 void __iomem *ctl;
69 void __iomem *ahb_base;
70 u32 ahb_window_size;
71 u32 ctl_val[ASPEED_SPI_MAX];
72 u32 clk_freq;
73 bool force_user_mode;
74 };
75
76 struct aspeed_spi_data {
77 u32 ctl0;
78 u32 max_cs;
79 bool hastype;
80 u32 mode_bits;
81 u32 we0;
82 u32 timing;
83 u32 hclk_mask;
84 u32 hdiv_max;
85 u32 min_window_size;
86 bool full_duplex;
87
88 phys_addr_t (*segment_start)(struct aspeed_spi *aspi, u32 reg);
89 phys_addr_t (*segment_end)(struct aspeed_spi *aspi, u32 reg);
90 u32 (*segment_reg)(struct aspeed_spi *aspi, phys_addr_t start,
91 phys_addr_t end);
92 int (*adjust_window)(struct aspeed_spi *aspi);
93 u32 (*get_clk_div)(struct aspeed_spi_chip *chip, u32 hz);
94 int (*calibrate)(struct aspeed_spi_chip *chip, u32 hdiv,
95 const u8 *golden_buf, u8 *test_buf);
96 };
97
98 #define ASPEED_SPI_MAX_NUM_CS 5
99
100 struct aspeed_spi {
101 const struct aspeed_spi_data *data;
102
103 void __iomem *regs;
104 phys_addr_t ahb_base_phy;
105 u32 ahb_window_size;
106 u32 num_cs;
107 struct device *dev;
108
109 struct clk *clk;
110 u32 clk_freq;
111 u8 cs_change;
112
113 struct aspeed_spi_chip chips[ASPEED_SPI_MAX_NUM_CS];
114 };
115
aspeed_spi_get_io_mode(const struct spi_mem_op * op)116 static u32 aspeed_spi_get_io_mode(const struct spi_mem_op *op)
117 {
118 switch (op->data.buswidth) {
119 case 1:
120 return CTRL_IO_SINGLE_DATA;
121 case 2:
122 return CTRL_IO_DUAL_DATA;
123 case 4:
124 return CTRL_IO_QUAD_DATA;
125 default:
126 return CTRL_IO_SINGLE_DATA;
127 }
128 }
129
aspeed_spi_set_io_mode(struct aspeed_spi_chip * chip,u32 io_mode)130 static void aspeed_spi_set_io_mode(struct aspeed_spi_chip *chip, u32 io_mode)
131 {
132 u32 ctl;
133
134 if (io_mode > 0) {
135 ctl = readl(chip->ctl) & ~CTRL_IO_MODE_MASK;
136 ctl |= io_mode;
137 writel(ctl, chip->ctl);
138 }
139 }
140
aspeed_spi_start_user(struct aspeed_spi_chip * chip)141 static void aspeed_spi_start_user(struct aspeed_spi_chip *chip)
142 {
143 u32 ctl = chip->ctl_val[ASPEED_SPI_BASE];
144
145 ctl |= CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
146 writel(ctl, chip->ctl);
147
148 ctl &= ~CTRL_CE_STOP_ACTIVE;
149 writel(ctl, chip->ctl);
150 }
151
aspeed_spi_stop_user(struct aspeed_spi_chip * chip)152 static void aspeed_spi_stop_user(struct aspeed_spi_chip *chip)
153 {
154 u32 ctl = chip->ctl_val[ASPEED_SPI_READ] |
155 CTRL_IO_MODE_USER | CTRL_CE_STOP_ACTIVE;
156
157 writel(ctl, chip->ctl);
158
159 /* Restore defaults */
160 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
161 }
162
aspeed_spi_read_from_ahb(void * buf,void __iomem * src,size_t len)163 static int aspeed_spi_read_from_ahb(void *buf, void __iomem *src, size_t len)
164 {
165 size_t offset = 0;
166
167 if (IS_ALIGNED((uintptr_t)src, sizeof(uintptr_t)) &&
168 IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
169 ioread32_rep(src, buf, len >> 2);
170 offset = len & ~0x3;
171 len -= offset;
172 }
173 ioread8_rep(src, (u8 *)buf + offset, len);
174 return 0;
175 }
176
aspeed_spi_write_to_ahb(void __iomem * dst,const void * buf,size_t len)177 static int aspeed_spi_write_to_ahb(void __iomem *dst, const void *buf, size_t len)
178 {
179 size_t offset = 0;
180
181 if (IS_ALIGNED((uintptr_t)dst, sizeof(uintptr_t)) &&
182 IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) {
183 iowrite32_rep(dst, buf, len >> 2);
184 offset = len & ~0x3;
185 len -= offset;
186 }
187 iowrite8_rep(dst, (const u8 *)buf + offset, len);
188 return 0;
189 }
190
aspeed_spi_send_cmd_addr(struct aspeed_spi_chip * chip,u8 addr_nbytes,u64 offset,u32 opcode)191 static int aspeed_spi_send_cmd_addr(struct aspeed_spi_chip *chip, u8 addr_nbytes,
192 u64 offset, u32 opcode)
193 {
194 __be32 temp;
195 u32 cmdaddr;
196
197 switch (addr_nbytes) {
198 case 3:
199 cmdaddr = offset & 0xFFFFFF;
200 cmdaddr |= opcode << 24;
201
202 temp = cpu_to_be32(cmdaddr);
203 aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
204 break;
205 case 4:
206 temp = cpu_to_be32(offset);
207 aspeed_spi_write_to_ahb(chip->ahb_base, &opcode, 1);
208 aspeed_spi_write_to_ahb(chip->ahb_base, &temp, 4);
209 break;
210 default:
211 WARN_ONCE(1, "Unexpected address width %u", addr_nbytes);
212 return -EOPNOTSUPP;
213 }
214 return 0;
215 }
216
aspeed_spi_read_reg(struct aspeed_spi_chip * chip,const struct spi_mem_op * op)217 static int aspeed_spi_read_reg(struct aspeed_spi_chip *chip,
218 const struct spi_mem_op *op)
219 {
220 aspeed_spi_start_user(chip);
221 aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
222 aspeed_spi_read_from_ahb(op->data.buf.in,
223 chip->ahb_base, op->data.nbytes);
224 aspeed_spi_stop_user(chip);
225 return 0;
226 }
227
aspeed_spi_write_reg(struct aspeed_spi_chip * chip,const struct spi_mem_op * op)228 static int aspeed_spi_write_reg(struct aspeed_spi_chip *chip,
229 const struct spi_mem_op *op)
230 {
231 aspeed_spi_start_user(chip);
232 aspeed_spi_write_to_ahb(chip->ahb_base, &op->cmd.opcode, 1);
233 aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out,
234 op->data.nbytes);
235 aspeed_spi_stop_user(chip);
236 return 0;
237 }
238
aspeed_spi_read_user(struct aspeed_spi_chip * chip,const struct spi_mem_op * op,u64 offset,size_t len,void * buf)239 static ssize_t aspeed_spi_read_user(struct aspeed_spi_chip *chip,
240 const struct spi_mem_op *op,
241 u64 offset, size_t len, void *buf)
242 {
243 int io_mode = aspeed_spi_get_io_mode(op);
244 u8 dummy = 0xFF;
245 int i;
246 int ret;
247
248 aspeed_spi_start_user(chip);
249
250 ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, offset, op->cmd.opcode);
251 if (ret < 0)
252 goto stop_user;
253
254 if (op->dummy.buswidth && op->dummy.nbytes) {
255 for (i = 0; i < op->dummy.nbytes / op->dummy.buswidth; i++)
256 aspeed_spi_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy));
257 }
258
259 aspeed_spi_set_io_mode(chip, io_mode);
260
261 aspeed_spi_read_from_ahb(buf, chip->ahb_base, len);
262 stop_user:
263 aspeed_spi_stop_user(chip);
264 return ret;
265 }
266
aspeed_spi_write_user(struct aspeed_spi_chip * chip,const struct spi_mem_op * op)267 static ssize_t aspeed_spi_write_user(struct aspeed_spi_chip *chip,
268 const struct spi_mem_op *op)
269 {
270 int ret;
271 int io_mode = aspeed_spi_get_io_mode(op);
272
273 aspeed_spi_start_user(chip);
274 ret = aspeed_spi_send_cmd_addr(chip, op->addr.nbytes, op->addr.val, op->cmd.opcode);
275 if (ret < 0)
276 goto stop_user;
277
278 aspeed_spi_set_io_mode(chip, io_mode);
279
280 aspeed_spi_write_to_ahb(chip->ahb_base, op->data.buf.out, op->data.nbytes);
281 stop_user:
282 aspeed_spi_stop_user(chip);
283 return ret;
284 }
285
286 /* support for 1-1-1, 1-1-2 or 1-1-4 */
aspeed_spi_supports_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)287 static bool aspeed_spi_supports_mem_op(struct spi_mem *mem,
288 const struct spi_mem_op *op)
289 {
290 if (op->cmd.buswidth > 1)
291 return false;
292
293 if (op->addr.nbytes != 0) {
294 if (op->addr.buswidth > 1)
295 return false;
296 if (op->addr.nbytes < 3 || op->addr.nbytes > 4)
297 return false;
298 }
299
300 if (op->dummy.nbytes != 0) {
301 if (op->dummy.buswidth > 1 || op->dummy.nbytes > 7)
302 return false;
303 }
304
305 if (op->data.nbytes != 0 && op->data.buswidth > 4)
306 return false;
307
308 return spi_mem_default_supports_op(mem, op);
309 }
310
311 static const struct aspeed_spi_data ast2400_spi_data;
312
do_aspeed_spi_exec_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)313 static int do_aspeed_spi_exec_mem_op(struct spi_mem *mem,
314 const struct spi_mem_op *op)
315 {
316 struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->controller);
317 struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(mem->spi, 0)];
318 u32 addr_mode, addr_mode_backup;
319 u32 ctl_val;
320 int ret = 0;
321
322 addr_mode = readl(aspi->regs + CE_CTRL_REG);
323 addr_mode_backup = addr_mode;
324
325 ctl_val = chip->ctl_val[ASPEED_SPI_BASE];
326 ctl_val &= ~CTRL_IO_CMD_MASK;
327
328 ctl_val |= op->cmd.opcode << CTRL_COMMAND_SHIFT;
329
330 /* 4BYTE address mode */
331 if (op->addr.nbytes) {
332 if (op->addr.nbytes == 4)
333 addr_mode |= (0x11 << chip->cs);
334 else
335 addr_mode &= ~(0x11 << chip->cs);
336
337 if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
338 ctl_val |= CTRL_IO_ADDRESS_4B;
339 }
340
341 if (op->dummy.nbytes)
342 ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
343
344 if (op->data.nbytes)
345 ctl_val |= aspeed_spi_get_io_mode(op);
346
347 if (op->data.dir == SPI_MEM_DATA_OUT)
348 ctl_val |= CTRL_IO_MODE_WRITE;
349 else
350 ctl_val |= CTRL_IO_MODE_READ;
351
352 if (addr_mode != addr_mode_backup)
353 writel(addr_mode, aspi->regs + CE_CTRL_REG);
354 writel(ctl_val, chip->ctl);
355
356 if (op->data.dir == SPI_MEM_DATA_IN) {
357 if (!op->addr.nbytes)
358 ret = aspeed_spi_read_reg(chip, op);
359 else
360 ret = aspeed_spi_read_user(chip, op, op->addr.val,
361 op->data.nbytes, op->data.buf.in);
362 } else {
363 if (!op->addr.nbytes)
364 ret = aspeed_spi_write_reg(chip, op);
365 else
366 ret = aspeed_spi_write_user(chip, op);
367 }
368
369 /* Restore defaults */
370 if (addr_mode != addr_mode_backup)
371 writel(addr_mode_backup, aspi->regs + CE_CTRL_REG);
372 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
373 return ret;
374 }
375
aspeed_spi_exec_mem_op(struct spi_mem * mem,const struct spi_mem_op * op)376 static int aspeed_spi_exec_mem_op(struct spi_mem *mem,
377 const struct spi_mem_op *op)
378 {
379 int ret;
380
381 ret = do_aspeed_spi_exec_mem_op(mem, op);
382 if (ret)
383 dev_err(&mem->spi->dev, "operation failed: %d\n", ret);
384 return ret;
385 }
386
aspeed_spi_get_name(struct spi_mem * mem)387 static const char *aspeed_spi_get_name(struct spi_mem *mem)
388 {
389 struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->controller);
390 struct device *dev = aspi->dev;
391
392 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
393 spi_get_chipselect(mem->spi, 0));
394 }
395
aspeed_spi_set_window(struct aspeed_spi * aspi)396 static int aspeed_spi_set_window(struct aspeed_spi *aspi)
397 {
398 struct device *dev = aspi->dev;
399 off_t offset = 0;
400 phys_addr_t start;
401 phys_addr_t end;
402 void __iomem *seg_reg_base = aspi->regs + CE0_SEGMENT_ADDR_REG;
403 void __iomem *seg_reg;
404 u32 seg_val_backup;
405 u32 seg_val;
406 u32 cs;
407 size_t window_size;
408
409 for (cs = 0; cs < aspi->data->max_cs; cs++) {
410 if (aspi->chips[cs].ahb_base) {
411 devm_iounmap(dev, aspi->chips[cs].ahb_base);
412 aspi->chips[cs].ahb_base = NULL;
413 }
414 }
415
416 for (cs = 0; cs < aspi->data->max_cs; cs++) {
417 seg_reg = seg_reg_base + cs * 4;
418 seg_val_backup = readl(seg_reg);
419
420 start = aspi->ahb_base_phy + offset;
421 window_size = aspi->chips[cs].ahb_window_size;
422 end = start + window_size;
423
424 seg_val = aspi->data->segment_reg(aspi, start, end);
425 writel(seg_val, seg_reg);
426
427 /*
428 * Restore initial value if something goes wrong or the segment
429 * register is written protected.
430 */
431 if (seg_val != readl(seg_reg)) {
432 dev_warn(dev, "CE%d expected window [ 0x%.9llx - 0x%.9llx ] %zdMB\n",
433 cs, (u64)start, (u64)end - 1, window_size >> 20);
434 writel(seg_val_backup, seg_reg);
435 window_size = aspi->data->segment_end(aspi, seg_val_backup) -
436 aspi->data->segment_start(aspi, seg_val_backup);
437 aspi->chips[cs].ahb_window_size = window_size;
438 end = start + window_size;
439 }
440
441 if (window_size != 0)
442 dev_dbg(dev, "CE%d window [ 0x%.9llx - 0x%.9llx ] %zdMB\n",
443 cs, (u64)start, (u64)end - 1, window_size >> 20);
444 else
445 dev_dbg(dev, "CE%d window closed\n", cs);
446
447 offset += window_size;
448 if (offset > aspi->ahb_window_size) {
449 dev_err(dev, "CE%d offset value 0x%llx is too large.\n",
450 cs, (u64)offset);
451 return -ENOSPC;
452 }
453
454 /*
455 * No need to map the address deocding range when
456 * - window size is 0.
457 * - the CS is unused.
458 */
459 if (window_size == 0 || cs >= aspi->num_cs)
460 continue;
461
462 aspi->chips[cs].ahb_base =
463 devm_ioremap(aspi->dev, start, window_size);
464 if (!aspi->chips[cs].ahb_base) {
465 dev_err(aspi->dev,
466 "Fail to remap window [0x%.9llx - 0x%.9llx]\n",
467 (u64)start, (u64)end - 1);
468 return -ENOMEM;
469 }
470 }
471
472 return 0;
473 }
474
475 static const struct aspeed_spi_data ast2500_spi_data;
476 static const struct aspeed_spi_data ast2600_spi_data;
477 static const struct aspeed_spi_data ast2600_fmc_data;
478
aspeed_spi_chip_set_default_window(struct aspeed_spi * aspi)479 static int aspeed_spi_chip_set_default_window(struct aspeed_spi *aspi)
480 {
481 u32 cs;
482
483 /* No segment registers for the AST2400 SPI controller */
484 if (aspi->data == &ast2400_spi_data) {
485 aspi->chips[0].ahb_base = devm_ioremap(aspi->dev,
486 aspi->ahb_base_phy,
487 aspi->ahb_window_size);
488 aspi->chips[0].ahb_window_size = aspi->ahb_window_size;
489 return 0;
490 }
491
492 /* Assign the minimum window size to each CS */
493 for (cs = 0; cs < aspi->num_cs; cs++) {
494 aspi->chips[cs].ahb_window_size = aspi->data->min_window_size;
495 dev_dbg(aspi->dev, "CE%d default window [ 0x%.9llx - 0x%.9llx ]",
496 cs, (u64)(aspi->ahb_base_phy + aspi->data->min_window_size * cs),
497 (u64)(aspi->ahb_base_phy + aspi->data->min_window_size * cs - 1));
498 }
499
500 /* Close unused CS */
501 for (cs = aspi->num_cs; cs < aspi->data->max_cs; cs++)
502 aspi->chips[cs].ahb_window_size = 0;
503
504 if (aspi->data->adjust_window)
505 aspi->data->adjust_window(aspi);
506
507 return aspeed_spi_set_window(aspi);
508 }
509
510 /*
511 * As the flash size grows up, we need to trim some decoding
512 * size if needed for the sake of conforming the maximum
513 * decoding size. We trim the decoding size from the rear CS
514 * to avoid affecting the default boot up sequence, usually,
515 * from CS0. Notice, if a CS decoding size is trimmed,
516 * command mode may not work perfectly on that CS, but it only
517 * affect performance and the debug function.
518 */
aspeed_spi_trim_window_size(struct aspeed_spi * aspi)519 static int aspeed_spi_trim_window_size(struct aspeed_spi *aspi)
520 {
521 struct aspeed_spi_chip *chips = aspi->chips;
522 size_t total_sz;
523 int cs = aspi->data->max_cs - 1;
524 u32 i;
525 bool trimmed = false;
526
527 do {
528 total_sz = 0;
529 for (i = 0; i < aspi->data->max_cs; i++)
530 total_sz += chips[i].ahb_window_size;
531
532 if (cs < 0)
533 return -ENOMEM;
534
535 if (chips[cs].ahb_window_size <= aspi->data->min_window_size) {
536 cs--;
537 continue;
538 }
539
540 if (total_sz > aspi->ahb_window_size) {
541 chips[cs].ahb_window_size -=
542 aspi->data->min_window_size;
543 total_sz -= aspi->data->min_window_size;
544 /*
545 * If the ahb window size is ever trimmed, only user
546 * mode can be adopted to access the whole flash.
547 */
548 chips[cs].force_user_mode = true;
549 trimmed = true;
550 }
551 } while (total_sz > aspi->ahb_window_size);
552
553 if (trimmed) {
554 dev_warn(aspi->dev, "Window size after trimming:\n");
555 for (cs = 0; cs < aspi->data->max_cs; cs++) {
556 dev_warn(aspi->dev, "CE%d: 0x%08x\n",
557 cs, chips[cs].ahb_window_size);
558 }
559 }
560
561 return 0;
562 }
563
aspeed_adjust_window_ast2400(struct aspeed_spi * aspi)564 static int aspeed_adjust_window_ast2400(struct aspeed_spi *aspi)
565 {
566 int ret;
567 int cs;
568 struct aspeed_spi_chip *chips = aspi->chips;
569
570 /* Close unused CS. */
571 for (cs = aspi->num_cs; cs < aspi->data->max_cs; cs++)
572 chips[cs].ahb_window_size = 0;
573
574 ret = aspeed_spi_trim_window_size(aspi);
575 if (ret != 0)
576 return ret;
577
578 return 0;
579 }
580
581 /*
582 * For AST2500, the minimum address decoding size for each CS
583 * is 8MB. This address decoding size is mandatory for each
584 * CS no matter whether it will be used. This is a HW limitation.
585 */
aspeed_adjust_window_ast2500(struct aspeed_spi * aspi)586 static int aspeed_adjust_window_ast2500(struct aspeed_spi *aspi)
587 {
588 int ret;
589 int cs, i;
590 u32 cum_size, rem_size;
591 struct aspeed_spi_chip *chips = aspi->chips;
592
593 /* Assign min_window_sz to unused CS. */
594 for (cs = aspi->num_cs; cs < aspi->data->max_cs; cs++) {
595 if (chips[cs].ahb_window_size < aspi->data->min_window_size)
596 chips[cs].ahb_window_size =
597 aspi->data->min_window_size;
598 }
599
600 /*
601 * If command mode or normal mode is used by dirmap read, the start
602 * address of a window should be multiple of its related flash size.
603 * Namely, the total windows size from flash 0 to flash N should
604 * be multiple of the size of flash (N + 1).
605 */
606 for (cs = aspi->num_cs - 1; cs >= 0; cs--) {
607 cum_size = 0;
608 for (i = 0; i < cs; i++)
609 cum_size += chips[i].ahb_window_size;
610
611 rem_size = cum_size % chips[cs].ahb_window_size;
612 if (chips[cs].ahb_window_size != 0 && rem_size != 0)
613 chips[0].ahb_window_size +=
614 chips[cs].ahb_window_size - rem_size;
615 }
616
617 ret = aspeed_spi_trim_window_size(aspi);
618 if (ret != 0)
619 return ret;
620
621 /* The total window size of AST2500 SPI1 CS0 and CS1 must be 128MB */
622 if (aspi->data == &ast2500_spi_data)
623 chips[1].ahb_window_size =
624 0x08000000 - chips[0].ahb_window_size;
625
626 return 0;
627 }
628
aspeed_adjust_window_ast2600(struct aspeed_spi * aspi)629 static int aspeed_adjust_window_ast2600(struct aspeed_spi *aspi)
630 {
631 int ret;
632 int cs, i;
633 u32 cum_size, rem_size;
634 struct aspeed_spi_chip *chips = aspi->chips;
635
636 /* Close unused CS. */
637 for (cs = aspi->num_cs; cs < aspi->data->max_cs; cs++)
638 chips[cs].ahb_window_size = 0;
639
640 /*
641 * If command mode or normal mode is used by dirmap read, the start
642 * address of a window should be multiple of its related flash size.
643 * Namely, the total windows size from flash 0 to flash N should
644 * be multiple of the size of flash (N + 1).
645 */
646 for (cs = aspi->num_cs - 1; cs >= 0; cs--) {
647 cum_size = 0;
648 for (i = 0; i < cs; i++)
649 cum_size += chips[i].ahb_window_size;
650
651 rem_size = cum_size % chips[cs].ahb_window_size;
652 if (chips[cs].ahb_window_size != 0 && rem_size != 0)
653 chips[0].ahb_window_size +=
654 chips[cs].ahb_window_size - rem_size;
655 }
656
657 ret = aspeed_spi_trim_window_size(aspi);
658 if (ret != 0)
659 return ret;
660
661 return 0;
662 }
663
664 /*
665 * Yet to be done when possible :
666 * - Align mappings on flash size (we don't have the info)
667 * - ioremap each window, not strictly necessary since the overall window
668 * is correct.
669 */
aspeed_spi_chip_adjust_window(struct aspeed_spi_chip * chip,u32 local_offset,u32 size)670 static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
671 u32 local_offset, u32 size)
672 {
673 struct aspeed_spi *aspi = chip->aspi;
674 int ret;
675
676 /* No segment registers for the AST2400 SPI controller */
677 if (aspi->data == &ast2400_spi_data)
678 return 0;
679
680 /* Adjust this chip window */
681 aspi->chips[chip->cs].ahb_window_size = size;
682
683 /* Adjust the overall windows size regarding each platform */
684 if (aspi->data->adjust_window)
685 aspi->data->adjust_window(aspi);
686
687 ret = aspeed_spi_set_window(aspi);
688 if (ret)
689 return ret;
690
691 return 0;
692 }
693
694 static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip);
695
aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc * desc)696 static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
697 {
698 struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->controller);
699 struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)];
700 struct spi_mem_op *op = &desc->info.op_tmpl;
701 u32 ctl_val;
702 int ret = 0;
703
704 dev_dbg(aspi->dev,
705 "CE%d %s dirmap [ 0x%.8llx - 0x%.8llx ] OP %#x mode:%d.%d.%d.%d naddr:%#x ndummies:%#x\n",
706 chip->cs, op->data.dir == SPI_MEM_DATA_IN ? "read" : "write",
707 desc->info.offset, desc->info.offset + desc->info.length,
708 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
709 op->dummy.buswidth, op->data.buswidth,
710 op->addr.nbytes, op->dummy.nbytes);
711
712 chip->clk_freq = desc->mem->spi->max_speed_hz;
713
714 /* Only for reads */
715 if (op->data.dir != SPI_MEM_DATA_IN)
716 return -EOPNOTSUPP;
717
718 aspeed_spi_chip_adjust_window(chip, desc->info.offset, desc->info.length);
719
720 if (desc->info.length > chip->ahb_window_size)
721 dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
722 chip->cs, chip->ahb_window_size >> 20);
723
724 /* Define the default IO read settings */
725 ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK;
726 ctl_val |= aspeed_spi_get_io_mode(op) |
727 op->cmd.opcode << CTRL_COMMAND_SHIFT |
728 CTRL_IO_MODE_READ;
729
730 if (op->dummy.nbytes)
731 ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
732
733 /* Tune 4BYTE address mode */
734 if (op->addr.nbytes) {
735 u32 addr_mode = readl(aspi->regs + CE_CTRL_REG);
736
737 if (op->addr.nbytes == 4)
738 addr_mode |= (0x11 << chip->cs);
739 else
740 addr_mode &= ~(0x11 << chip->cs);
741 writel(addr_mode, aspi->regs + CE_CTRL_REG);
742
743 /* AST2400 SPI controller sets 4BYTE address mode in
744 * CE0 Control Register
745 */
746 if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
747 ctl_val |= CTRL_IO_ADDRESS_4B;
748 }
749
750 /* READ mode is the controller default setting */
751 chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
752 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
753
754 ret = aspeed_spi_do_calibration(chip);
755
756 dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
757 chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
758
759 return ret;
760 }
761
aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc * desc,u64 offset,size_t len,void * buf)762 static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
763 u64 offset, size_t len, void *buf)
764 {
765 struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->controller);
766 struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)];
767
768 /* Switch to USER command mode if mapping window is too small */
769 if (chip->ahb_window_size < offset + len || chip->force_user_mode) {
770 int ret;
771
772 ret = aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf);
773 if (ret < 0)
774 return ret;
775 } else {
776 memcpy_fromio(buf, chip->ahb_base + offset, len);
777 }
778
779 return len;
780 }
781
782 static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
783 .supports_op = aspeed_spi_supports_mem_op,
784 .exec_op = aspeed_spi_exec_mem_op,
785 .get_name = aspeed_spi_get_name,
786 .dirmap_create = aspeed_spi_dirmap_create,
787 .dirmap_read = aspeed_spi_dirmap_read,
788 };
789
aspeed_spi_chip_set_type(struct aspeed_spi * aspi,unsigned int cs,int type)790 static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
791 {
792 u32 reg;
793
794 reg = readl(aspi->regs + CONFIG_REG);
795 reg &= ~(0x3 << (cs * 2));
796 reg |= type << (cs * 2);
797 writel(reg, aspi->regs + CONFIG_REG);
798 }
799
aspeed_spi_chip_enable(struct aspeed_spi * aspi,unsigned int cs,bool enable)800 static void aspeed_spi_chip_enable(struct aspeed_spi *aspi, unsigned int cs, bool enable)
801 {
802 u32 we_bit = BIT(aspi->data->we0 + cs);
803 u32 reg = readl(aspi->regs + CONFIG_REG);
804
805 if (enable)
806 reg |= we_bit;
807 else
808 reg &= ~we_bit;
809 writel(reg, aspi->regs + CONFIG_REG);
810 }
811
aspeed_spi_setup(struct spi_device * spi)812 static int aspeed_spi_setup(struct spi_device *spi)
813 {
814 struct aspeed_spi *aspi = spi_controller_get_devdata(spi->controller);
815 const struct aspeed_spi_data *data = aspi->data;
816 unsigned int cs = spi_get_chipselect(spi, 0);
817 struct aspeed_spi_chip *chip = &aspi->chips[cs];
818
819 chip->aspi = aspi;
820 chip->cs = cs;
821 chip->ctl = aspi->regs + data->ctl0 + cs * 4;
822
823 /* The driver only supports SPI type flash */
824 if (data->hastype)
825 aspeed_spi_chip_set_type(aspi, cs, CONFIG_TYPE_SPI);
826
827 aspeed_spi_chip_enable(aspi, cs, true);
828
829 chip->ctl_val[ASPEED_SPI_BASE] = CTRL_CE_STOP_ACTIVE | CTRL_IO_MODE_USER;
830
831 dev_dbg(aspi->dev, "CE%d setup done\n", cs);
832 return 0;
833 }
834
aspeed_spi_cleanup(struct spi_device * spi)835 static void aspeed_spi_cleanup(struct spi_device *spi)
836 {
837 struct aspeed_spi *aspi = spi_controller_get_devdata(spi->controller);
838 unsigned int cs = spi_get_chipselect(spi, 0);
839
840 aspeed_spi_chip_enable(aspi, cs, false);
841
842 dev_dbg(aspi->dev, "CE%d cleanup done\n", cs);
843 }
844
aspeed_spi_enable(struct aspeed_spi * aspi,bool enable)845 static void aspeed_spi_enable(struct aspeed_spi *aspi, bool enable)
846 {
847 int cs;
848
849 for (cs = 0; cs < aspi->data->max_cs; cs++)
850 aspeed_spi_chip_enable(aspi, cs, enable);
851 }
852
aspeed_spi_user_prepare_msg(struct spi_controller * ctlr,struct spi_message * msg)853 static int aspeed_spi_user_prepare_msg(struct spi_controller *ctlr,
854 struct spi_message *msg)
855 {
856 struct aspeed_spi *aspi =
857 (struct aspeed_spi *)spi_controller_get_devdata(ctlr);
858 const struct aspeed_spi_data *data = aspi->data;
859 struct spi_device *spi = msg->spi;
860 u32 cs = spi_get_chipselect(spi, 0);
861 struct aspeed_spi_chip *chip = &aspi->chips[cs];
862 u32 ctrl_val;
863 u32 clk_div = data->get_clk_div(chip, spi->max_speed_hz);
864
865 ctrl_val = chip->ctl_val[ASPEED_SPI_BASE];
866 ctrl_val &= ~CTRL_IO_MODE_MASK & data->hclk_mask;
867 ctrl_val |= clk_div;
868 chip->ctl_val[ASPEED_SPI_BASE] = ctrl_val;
869
870 if (aspi->cs_change == 0)
871 aspeed_spi_start_user(chip);
872
873 return 0;
874 }
875
aspeed_spi_user_unprepare_msg(struct spi_controller * ctlr,struct spi_message * msg)876 static int aspeed_spi_user_unprepare_msg(struct spi_controller *ctlr,
877 struct spi_message *msg)
878 {
879 struct aspeed_spi *aspi =
880 (struct aspeed_spi *)spi_controller_get_devdata(ctlr);
881 struct spi_device *spi = msg->spi;
882 u32 cs = spi_get_chipselect(spi, 0);
883 struct aspeed_spi_chip *chip = &aspi->chips[cs];
884
885 if (aspi->cs_change == 0)
886 aspeed_spi_stop_user(chip);
887
888 return 0;
889 }
890
aspeed_spi_user_transfer_tx(struct aspeed_spi * aspi,struct spi_device * spi,const u8 * tx_buf,u8 * rx_buf,void * dst,u32 len)891 static void aspeed_spi_user_transfer_tx(struct aspeed_spi *aspi,
892 struct spi_device *spi,
893 const u8 *tx_buf, u8 *rx_buf,
894 void *dst, u32 len)
895 {
896 const struct aspeed_spi_data *data = aspi->data;
897 bool full_duplex_transfer = data->full_duplex && tx_buf == rx_buf;
898 u32 i;
899
900 if (full_duplex_transfer &&
901 !!(spi->mode & (SPI_TX_DUAL | SPI_TX_QUAD |
902 SPI_RX_DUAL | SPI_RX_QUAD))) {
903 dev_err(aspi->dev,
904 "full duplex is only supported for single IO mode\n");
905 return;
906 }
907
908 for (i = 0; i < len; i++) {
909 writeb(tx_buf[i], dst);
910 if (full_duplex_transfer)
911 rx_buf[i] = readb(aspi->regs + FULL_DUPLEX_RX_DATA);
912 }
913 }
914
aspeed_spi_user_transfer(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * xfer)915 static int aspeed_spi_user_transfer(struct spi_controller *ctlr,
916 struct spi_device *spi,
917 struct spi_transfer *xfer)
918 {
919 struct aspeed_spi *aspi =
920 (struct aspeed_spi *)spi_controller_get_devdata(ctlr);
921 u32 cs = spi_get_chipselect(spi, 0);
922 struct aspeed_spi_chip *chip = &aspi->chips[cs];
923 void __iomem *ahb_base = aspi->chips[cs].ahb_base;
924 const u8 *tx_buf = xfer->tx_buf;
925 u8 *rx_buf = xfer->rx_buf;
926
927 dev_dbg(aspi->dev,
928 "[cs%d] xfer: width %d, len %u, tx %p, rx %p\n",
929 cs, xfer->bits_per_word, xfer->len,
930 tx_buf, rx_buf);
931
932 if (tx_buf) {
933 if (spi->mode & SPI_TX_DUAL)
934 aspeed_spi_set_io_mode(chip, CTRL_IO_DUAL_DATA);
935 else if (spi->mode & SPI_TX_QUAD)
936 aspeed_spi_set_io_mode(chip, CTRL_IO_QUAD_DATA);
937
938 aspeed_spi_user_transfer_tx(aspi, spi, tx_buf, rx_buf,
939 (void *)ahb_base, xfer->len);
940 }
941
942 if (rx_buf && rx_buf != tx_buf) {
943 if (spi->mode & SPI_RX_DUAL)
944 aspeed_spi_set_io_mode(chip, CTRL_IO_DUAL_DATA);
945 else if (spi->mode & SPI_RX_QUAD)
946 aspeed_spi_set_io_mode(chip, CTRL_IO_QUAD_DATA);
947
948 ioread8_rep(ahb_base, rx_buf, xfer->len);
949 }
950
951 xfer->error = 0;
952 aspi->cs_change = xfer->cs_change;
953
954 return 0;
955 }
956
aspeed_spi_probe(struct platform_device * pdev)957 static int aspeed_spi_probe(struct platform_device *pdev)
958 {
959 struct device *dev = &pdev->dev;
960 const struct aspeed_spi_data *data;
961 struct spi_controller *ctlr;
962 struct aspeed_spi *aspi;
963 struct resource *res;
964 int ret;
965
966 data = of_device_get_match_data(&pdev->dev);
967 if (!data)
968 return -ENODEV;
969
970 ctlr = devm_spi_alloc_host(dev, sizeof(*aspi));
971 if (!ctlr)
972 return -ENOMEM;
973
974 aspi = spi_controller_get_devdata(ctlr);
975 platform_set_drvdata(pdev, ctlr);
976 aspi->data = data;
977 aspi->dev = dev;
978
979 aspi->regs = devm_platform_ioremap_resource(pdev, 0);
980 if (IS_ERR(aspi->regs))
981 return PTR_ERR(aspi->regs);
982
983 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
984 if (!res) {
985 dev_err(dev, "missing AHB memory\n");
986 return -EINVAL;
987 }
988
989 aspi->ahb_window_size = resource_size(res);
990 aspi->ahb_base_phy = res->start;
991
992 aspi->clk = devm_clk_get_enabled(&pdev->dev, NULL);
993 if (IS_ERR(aspi->clk)) {
994 dev_err(dev, "missing clock\n");
995 return PTR_ERR(aspi->clk);
996 }
997
998 aspi->clk_freq = clk_get_rate(aspi->clk);
999 if (!aspi->clk_freq) {
1000 dev_err(dev, "invalid clock\n");
1001 return -EINVAL;
1002 }
1003
1004 /* IRQ is for DMA, which the driver doesn't support yet */
1005
1006 ctlr->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | data->mode_bits;
1007 ctlr->bus_num = pdev->id;
1008 ctlr->mem_ops = &aspeed_spi_mem_ops;
1009 ctlr->setup = aspeed_spi_setup;
1010 ctlr->cleanup = aspeed_spi_cleanup;
1011 ctlr->num_chipselect = of_get_available_child_count(dev->of_node);
1012 ctlr->prepare_message = aspeed_spi_user_prepare_msg;
1013 ctlr->unprepare_message = aspeed_spi_user_unprepare_msg;
1014 ctlr->transfer_one = aspeed_spi_user_transfer;
1015
1016 aspi->num_cs = ctlr->num_chipselect;
1017
1018 ret = aspeed_spi_chip_set_default_window(aspi);
1019 if (ret) {
1020 dev_err(&pdev->dev, "fail to set default window\n");
1021 return ret;
1022 }
1023
1024 ret = spi_register_controller(ctlr);
1025 if (ret)
1026 dev_err(&pdev->dev, "spi_register_controller failed\n");
1027
1028 return ret;
1029 }
1030
aspeed_spi_remove(struct platform_device * pdev)1031 static void aspeed_spi_remove(struct platform_device *pdev)
1032 {
1033 struct spi_controller *ctlr = platform_get_drvdata(pdev);
1034 struct aspeed_spi *aspi = spi_controller_get_devdata(ctlr);
1035
1036 spi_unregister_controller(ctlr);
1037
1038 aspeed_spi_enable(aspi, false);
1039 }
1040
1041 /*
1042 * AHB mappings
1043 */
1044
1045 /*
1046 * The Segment Registers of the AST2400 and AST2500 use a 8MB unit.
1047 * The address range is encoded with absolute addresses in the overall
1048 * mapping window.
1049 */
aspeed_spi_segment_start(struct aspeed_spi * aspi,u32 reg)1050 static phys_addr_t aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg)
1051 {
1052 return ((reg >> 16) & 0xFF) << 23;
1053 }
1054
aspeed_spi_segment_end(struct aspeed_spi * aspi,u32 reg)1055 static phys_addr_t aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg)
1056 {
1057 return ((reg >> 24) & 0xFF) << 23;
1058 }
1059
aspeed_spi_segment_reg(struct aspeed_spi * aspi,phys_addr_t start,phys_addr_t end)1060 static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi,
1061 phys_addr_t start, phys_addr_t end)
1062 {
1063 return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24);
1064 }
1065
1066 /*
1067 * The Segment Registers of the AST2600 use a 1MB unit. The address
1068 * range is encoded with offsets in the overall mapping window.
1069 */
1070
1071 #define AST2600_SEG_ADDR_MASK 0x0ff00000
1072
aspeed_spi_segment_ast2600_start(struct aspeed_spi * aspi,u32 reg)1073 static phys_addr_t aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi,
1074 u32 reg)
1075 {
1076 u32 start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK;
1077
1078 return aspi->ahb_base_phy + start_offset;
1079 }
1080
aspeed_spi_segment_ast2600_end(struct aspeed_spi * aspi,u32 reg)1081 static phys_addr_t aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi,
1082 u32 reg)
1083 {
1084 u32 end_offset = reg & AST2600_SEG_ADDR_MASK;
1085
1086 /* segment is disabled */
1087 if (!end_offset)
1088 return aspi->ahb_base_phy;
1089
1090 return aspi->ahb_base_phy + end_offset + 0x100000;
1091 }
1092
aspeed_spi_segment_ast2600_reg(struct aspeed_spi * aspi,phys_addr_t start,phys_addr_t end)1093 static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
1094 phys_addr_t start, phys_addr_t end)
1095 {
1096 /* disable zero size segments */
1097 if (start == end)
1098 return 0;
1099
1100 return ((start & AST2600_SEG_ADDR_MASK) >> 16) |
1101 ((end - 1) & AST2600_SEG_ADDR_MASK);
1102 }
1103
1104 /* The Segment Registers of the AST2700 use a 64KB unit. */
1105 #define AST2700_SEG_ADDR_MASK 0x7fff0000
1106
aspeed_spi_segment_ast2700_start(struct aspeed_spi * aspi,u32 reg)1107 static phys_addr_t aspeed_spi_segment_ast2700_start(struct aspeed_spi *aspi,
1108 u32 reg)
1109 {
1110 u64 start_offset = (reg << 16) & AST2700_SEG_ADDR_MASK;
1111
1112 if (!start_offset)
1113 return aspi->ahb_base_phy;
1114
1115 return aspi->ahb_base_phy + start_offset;
1116 }
1117
aspeed_spi_segment_ast2700_end(struct aspeed_spi * aspi,u32 reg)1118 static phys_addr_t aspeed_spi_segment_ast2700_end(struct aspeed_spi *aspi,
1119 u32 reg)
1120 {
1121 u64 end_offset = reg & AST2700_SEG_ADDR_MASK;
1122
1123 if (!end_offset)
1124 return aspi->ahb_base_phy;
1125
1126 return aspi->ahb_base_phy + end_offset;
1127 }
1128
aspeed_spi_segment_ast2700_reg(struct aspeed_spi * aspi,phys_addr_t start,phys_addr_t end)1129 static u32 aspeed_spi_segment_ast2700_reg(struct aspeed_spi *aspi,
1130 phys_addr_t start, phys_addr_t end)
1131 {
1132 if (start == end)
1133 return 0;
1134
1135 return (u32)(((start & AST2700_SEG_ADDR_MASK) >> 16) |
1136 (end & AST2700_SEG_ADDR_MASK));
1137 }
1138
1139 /*
1140 * Read timing compensation sequences
1141 */
1142
1143 #define CALIBRATE_BUF_SIZE SZ_16K
1144
aspeed_spi_check_reads(struct aspeed_spi_chip * chip,const u8 * golden_buf,u8 * test_buf)1145 static bool aspeed_spi_check_reads(struct aspeed_spi_chip *chip,
1146 const u8 *golden_buf, u8 *test_buf)
1147 {
1148 int i;
1149
1150 for (i = 0; i < 10; i++) {
1151 memcpy_fromio(test_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
1152 if (memcmp(test_buf, golden_buf, CALIBRATE_BUF_SIZE) != 0) {
1153 #if defined(VERBOSE_DEBUG)
1154 print_hex_dump_bytes(DEVICE_NAME " fail: ", DUMP_PREFIX_NONE,
1155 test_buf, 0x100);
1156 #endif
1157 return false;
1158 }
1159 }
1160 return true;
1161 }
1162
1163 #define FREAD_TPASS(i) (((i) / 2) | (((i) & 1) ? 0 : 8))
1164
1165 /*
1166 * The timing register is shared by all devices. Only update for CE0.
1167 */
aspeed_spi_calibrate(struct aspeed_spi_chip * chip,u32 hdiv,const u8 * golden_buf,u8 * test_buf)1168 static int aspeed_spi_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
1169 const u8 *golden_buf, u8 *test_buf)
1170 {
1171 struct aspeed_spi *aspi = chip->aspi;
1172 const struct aspeed_spi_data *data = aspi->data;
1173 int i;
1174 int good_pass = -1, pass_count = 0;
1175 u32 shift = (hdiv - 1) << 2;
1176 u32 mask = ~(0xfu << shift);
1177 u32 fread_timing_val = 0;
1178
1179 /* Try HCLK delay 0..5, each one with/without delay and look for a
1180 * good pair.
1181 */
1182 for (i = 0; i < 12; i++) {
1183 bool pass;
1184
1185 if (chip->cs == 0) {
1186 fread_timing_val &= mask;
1187 fread_timing_val |= FREAD_TPASS(i) << shift;
1188 writel(fread_timing_val, aspi->regs + data->timing);
1189 }
1190 pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
1191 dev_dbg(aspi->dev,
1192 " * [%08x] %d HCLK delay, %dns DI delay : %s",
1193 fread_timing_val, i / 2, (i & 1) ? 0 : 4,
1194 pass ? "PASS" : "FAIL");
1195 if (pass) {
1196 pass_count++;
1197 if (pass_count == 3) {
1198 good_pass = i - 1;
1199 break;
1200 }
1201 } else {
1202 pass_count = 0;
1203 }
1204 }
1205
1206 /* No good setting for this frequency */
1207 if (good_pass < 0)
1208 return -1;
1209
1210 /* We have at least one pass of margin, let's use first pass */
1211 if (chip->cs == 0) {
1212 fread_timing_val &= mask;
1213 fread_timing_val |= FREAD_TPASS(good_pass) << shift;
1214 writel(fread_timing_val, aspi->regs + data->timing);
1215 }
1216 dev_dbg(aspi->dev, " * -> good is pass %d [0x%08x]",
1217 good_pass, fread_timing_val);
1218 return 0;
1219 }
1220
aspeed_spi_check_calib_data(const u8 * test_buf,u32 size)1221 static bool aspeed_spi_check_calib_data(const u8 *test_buf, u32 size)
1222 {
1223 const u32 *tb32 = (const u32 *)test_buf;
1224 u32 i, cnt = 0;
1225
1226 /* We check if we have enough words that are neither all 0
1227 * nor all 1's so the calibration can be considered valid.
1228 *
1229 * I use an arbitrary threshold for now of 64
1230 */
1231 size >>= 2;
1232 for (i = 0; i < size; i++) {
1233 if (tb32[i] != 0 && tb32[i] != 0xffffffff)
1234 cnt++;
1235 }
1236 return cnt >= 64;
1237 }
1238
1239 static const u32 aspeed_spi_hclk_divs[] = {
1240 /* HCLK, HCLK/2, HCLK/3, HCLK/4, HCLK/5, ..., HCLK/16 */
1241 0xf, 0x7, 0xe, 0x6, 0xd,
1242 0x5, 0xc, 0x4, 0xb, 0x3,
1243 0xa, 0x2, 0x9, 0x1, 0x8,
1244 0x0
1245 };
1246
1247 #define ASPEED_SPI_HCLK_DIV(i) \
1248 (aspeed_spi_hclk_divs[(i) - 1] << CTRL_FREQ_SEL_SHIFT)
1249
1250 /* Transfer maximum clock frequency to register setting */
aspeed_get_clk_div_ast2400(struct aspeed_spi_chip * chip,u32 max_hz)1251 static u32 aspeed_get_clk_div_ast2400(struct aspeed_spi_chip *chip,
1252 u32 max_hz)
1253 {
1254 struct device *dev = chip->aspi->dev;
1255 u32 hclk_clk = chip->aspi->clk_freq;
1256 u32 div_ctl = 0;
1257 u32 i;
1258 bool found = false;
1259
1260 /* FMC/SPIR10[11:8] */
1261 for (i = 1; i <= ARRAY_SIZE(aspeed_spi_hclk_divs); i++) {
1262 if (hclk_clk / i <= max_hz) {
1263 found = true;
1264 break;
1265 }
1266 }
1267
1268 if (found) {
1269 div_ctl = ASPEED_SPI_HCLK_DIV(i);
1270 chip->clk_freq = hclk_clk / i;
1271 }
1272
1273 dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n",
1274 found ? "yes" : "no", hclk_clk, max_hz);
1275
1276 if (found) {
1277 dev_dbg(dev, "h_div: 0x%08x, speed: %d\n",
1278 div_ctl, chip->clk_freq);
1279 }
1280
1281 return div_ctl;
1282 }
1283
aspeed_get_clk_div_ast2500(struct aspeed_spi_chip * chip,u32 max_hz)1284 static u32 aspeed_get_clk_div_ast2500(struct aspeed_spi_chip *chip,
1285 u32 max_hz)
1286 {
1287 struct device *dev = chip->aspi->dev;
1288 u32 hclk_clk = chip->aspi->clk_freq;
1289 u32 div_ctl = 0;
1290 u32 i;
1291 bool found = false;
1292
1293 /* FMC/SPIR10[11:8] */
1294 for (i = 1; i <= ARRAY_SIZE(aspeed_spi_hclk_divs); i++) {
1295 if (hclk_clk / i <= max_hz) {
1296 found = true;
1297 chip->clk_freq = hclk_clk / i;
1298 break;
1299 }
1300 }
1301
1302 if (found) {
1303 div_ctl = ASPEED_SPI_HCLK_DIV(i);
1304 goto end;
1305 }
1306
1307 for (i = 1; i <= ARRAY_SIZE(aspeed_spi_hclk_divs); i++) {
1308 if (hclk_clk / (i * 4) <= max_hz) {
1309 found = true;
1310 chip->clk_freq = hclk_clk / (i * 4);
1311 break;
1312 }
1313 }
1314
1315 if (found)
1316 div_ctl = BIT(13) | ASPEED_SPI_HCLK_DIV(i);
1317
1318 end:
1319 dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n",
1320 found ? "yes" : "no", hclk_clk, max_hz);
1321
1322 if (found) {
1323 dev_dbg(dev, "h_div: 0x%08x, speed: %d\n",
1324 div_ctl, chip->clk_freq);
1325 }
1326
1327 return div_ctl;
1328 }
1329
aspeed_get_clk_div_ast2600(struct aspeed_spi_chip * chip,u32 max_hz)1330 static u32 aspeed_get_clk_div_ast2600(struct aspeed_spi_chip *chip,
1331 u32 max_hz)
1332 {
1333 struct device *dev = chip->aspi->dev;
1334 u32 hclk_clk = chip->aspi->clk_freq;
1335 u32 div_ctl = 0;
1336 u32 i, j;
1337 bool found = false;
1338
1339 /* FMC/SPIR10[27:24] */
1340 for (j = 0; j < 16; j++) {
1341 /* FMC/SPIR10[11:8] */
1342 for (i = 1; i <= ARRAY_SIZE(aspeed_spi_hclk_divs); i++) {
1343 if (j == 0 && i == 1)
1344 continue;
1345
1346 if (hclk_clk / (j * 16 + i) <= max_hz) {
1347 found = true;
1348 break;
1349 }
1350 }
1351
1352 if (found) {
1353 div_ctl = ((j << 24) | ASPEED_SPI_HCLK_DIV(i));
1354 chip->clk_freq = hclk_clk / (j * 16 + i);
1355 break;
1356 }
1357 }
1358
1359 dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n",
1360 found ? "yes" : "no", hclk_clk, max_hz);
1361
1362 if (found) {
1363 dev_dbg(dev, "h_div: 0x%08x, speed: %d\n",
1364 div_ctl, chip->clk_freq);
1365 }
1366
1367 return div_ctl;
1368 }
1369
aspeed_spi_do_calibration(struct aspeed_spi_chip * chip)1370 static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip)
1371 {
1372 struct aspeed_spi *aspi = chip->aspi;
1373 const struct aspeed_spi_data *data = aspi->data;
1374 u32 ahb_freq = aspi->clk_freq;
1375 u32 max_freq = chip->clk_freq;
1376 bool exec_calib = false;
1377 u32 best_freq = 0;
1378 u32 ctl_val;
1379 u8 *golden_buf = NULL;
1380 u8 *test_buf = NULL;
1381 int i, rc;
1382 u32 div_ctl;
1383
1384 dev_dbg(aspi->dev, "calculate timing compensation - AHB freq: %d MHz",
1385 ahb_freq / 1000000);
1386
1387 /*
1388 * use the related low frequency to get check calibration data
1389 * and get golden data.
1390 */
1391 ctl_val = chip->ctl_val[ASPEED_SPI_READ] & data->hclk_mask;
1392 writel(ctl_val, chip->ctl);
1393
1394 test_buf = kzalloc(CALIBRATE_BUF_SIZE * 2, GFP_KERNEL);
1395 if (!test_buf)
1396 return -ENOMEM;
1397
1398 golden_buf = test_buf + CALIBRATE_BUF_SIZE;
1399
1400 memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE);
1401 if (!aspeed_spi_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) {
1402 dev_info(aspi->dev, "Calibration area too uniform, using low speed");
1403 goto end_calib;
1404 }
1405
1406 #if defined(VERBOSE_DEBUG)
1407 print_hex_dump_bytes(DEVICE_NAME " good: ", DUMP_PREFIX_NONE,
1408 golden_buf, 0x100);
1409 #endif
1410
1411 /* Now we iterate the HCLK dividers until we find our breaking point */
1412 for (i = 5; i > data->hdiv_max - 1; i--) {
1413 u32 tv, freq;
1414
1415 freq = ahb_freq / i;
1416 if (freq > max_freq)
1417 continue;
1418
1419 /* Set the timing */
1420 tv = chip->ctl_val[ASPEED_SPI_READ] | ASPEED_SPI_HCLK_DIV(i);
1421 writel(tv, chip->ctl);
1422 dev_dbg(aspi->dev, "Trying HCLK/%d [%08x] ...", i, tv);
1423 rc = data->calibrate(chip, i, golden_buf, test_buf);
1424 if (rc == 0)
1425 best_freq = freq;
1426
1427 exec_calib = true;
1428 }
1429
1430 end_calib:
1431 if (!exec_calib) {
1432 /* calibration process is not executed */
1433 dev_warn(aspi->dev, "Force to dts configuration %dkHz.\n",
1434 max_freq / 1000);
1435 div_ctl = data->get_clk_div(chip, max_freq);
1436 } else if (best_freq == 0) {
1437 /* calibration process is executed, but no good frequency */
1438 dev_warn(aspi->dev, "No good frequency, using dumb slow\n");
1439 div_ctl = 0;
1440 } else {
1441 dev_dbg(aspi->dev, "Found good read timings at %dMHz.\n",
1442 best_freq / 1000000);
1443 div_ctl = data->get_clk_div(chip, best_freq);
1444 }
1445
1446 /* Record the freq */
1447 for (i = 0; i < ASPEED_SPI_MAX; i++) {
1448 chip->ctl_val[i] = (chip->ctl_val[i] & data->hclk_mask) |
1449 div_ctl;
1450 }
1451
1452 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
1453 kfree(test_buf);
1454 return 0;
1455 }
1456
1457 #define TIMING_DELAY_DI BIT(3)
1458 #define TIMING_DELAY_HCYCLE_MAX 5
1459 #define TIMING_DELAY_INPUT_MAX 16
1460 #define TIMING_REG_AST2600(chip) \
1461 ((chip)->aspi->regs + (chip)->aspi->data->timing + \
1462 (chip)->cs * 4)
1463
1464 /*
1465 * This function returns the center point of the longest
1466 * continuous "pass" interval within the buffer. The interval
1467 * must contains the highest number of consecutive "pass"
1468 * results and not span across multiple rows.
1469 */
aspeed_spi_ast2600_optimized_timing(u32 rows,u32 cols,u8 buf[rows][cols])1470 static u32 aspeed_spi_ast2600_optimized_timing(u32 rows, u32 cols,
1471 u8 buf[rows][cols])
1472 {
1473 int r = 0, c = 0;
1474 int max = 0;
1475 int i, j;
1476
1477 for (i = 0; i < rows; i++) {
1478 for (j = 0; j < cols;) {
1479 int k = j;
1480
1481 while (k < cols && buf[i][k])
1482 k++;
1483
1484 if (k - j > max) {
1485 max = k - j;
1486 r = i;
1487 c = j + (k - j) / 2;
1488 }
1489
1490 j = k + 1;
1491 }
1492 }
1493
1494 return max > 4 ? r * cols + c : 0;
1495 }
1496
aspeed_spi_ast2600_calibrate(struct aspeed_spi_chip * chip,u32 hdiv,const u8 * golden_buf,u8 * test_buf)1497 static int aspeed_spi_ast2600_calibrate(struct aspeed_spi_chip *chip, u32 hdiv,
1498 const u8 *golden_buf, u8 *test_buf)
1499 {
1500 struct aspeed_spi *aspi = chip->aspi;
1501 int hcycle;
1502 int delay_ns;
1503 u32 shift = (hdiv - 2) << 3;
1504 u32 mask = ~(0xffu << shift);
1505 u32 fread_timing_val = 0;
1506 u8 calib_res[6][17] = {0};
1507 u32 calib_point;
1508
1509 for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) {
1510 bool pass = false;
1511
1512 fread_timing_val &= mask;
1513 fread_timing_val |= hcycle << shift;
1514
1515 /* no DI input delay first */
1516 writel(fread_timing_val, TIMING_REG_AST2600(chip));
1517 pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
1518 dev_dbg(aspi->dev,
1519 " * [%08x] %d HCLK delay, DI delay none : %s",
1520 fread_timing_val, hcycle, pass ? "PASS" : "FAIL");
1521 if (pass)
1522 calib_res[hcycle][0] = 1;
1523
1524 /* Add DI input delays */
1525 fread_timing_val &= mask;
1526 fread_timing_val |= (TIMING_DELAY_DI | hcycle) << shift;
1527
1528 for (delay_ns = 0; delay_ns < TIMING_DELAY_INPUT_MAX; delay_ns++) {
1529 fread_timing_val &= ~(0xfu << (4 + shift));
1530 fread_timing_val |= delay_ns << (4 + shift);
1531
1532 writel(fread_timing_val, TIMING_REG_AST2600(chip));
1533 pass = aspeed_spi_check_reads(chip, golden_buf, test_buf);
1534 dev_dbg(aspi->dev,
1535 " * [%08x] %d HCLK delay, DI delay %d.%dns : %s",
1536 fread_timing_val, hcycle, (delay_ns + 1) / 2,
1537 (delay_ns + 1) & 1 ? 5 : 5, pass ? "PASS" : "FAIL");
1538
1539 if (pass)
1540 calib_res[hcycle][delay_ns + 1] = 1;
1541 }
1542 }
1543
1544 calib_point = aspeed_spi_ast2600_optimized_timing(6, 17, calib_res);
1545 /* No good setting for this frequency */
1546 if (calib_point == 0)
1547 return -1;
1548
1549 hcycle = calib_point / 17;
1550 delay_ns = calib_point % 17;
1551
1552 fread_timing_val = (TIMING_DELAY_DI | hcycle | (delay_ns << 4)) << shift;
1553
1554 dev_dbg(aspi->dev, "timing val: %08x, final hcycle: %d, delay_ns: %d\n",
1555 fread_timing_val, hcycle, delay_ns);
1556
1557 writel(fread_timing_val, TIMING_REG_AST2600(chip));
1558
1559 return 0;
1560 }
1561
1562 /*
1563 * Platform definitions
1564 */
1565 static const struct aspeed_spi_data ast2400_fmc_data = {
1566 .max_cs = 5,
1567 .hastype = true,
1568 .we0 = 16,
1569 .ctl0 = CE0_CTRL_REG,
1570 .timing = CE0_TIMING_COMPENSATION_REG,
1571 .hclk_mask = 0xfffff0ff,
1572 .hdiv_max = 1,
1573 .min_window_size = 0x800000,
1574 .full_duplex = false,
1575 .calibrate = aspeed_spi_calibrate,
1576 .get_clk_div = aspeed_get_clk_div_ast2400,
1577 .segment_start = aspeed_spi_segment_start,
1578 .segment_end = aspeed_spi_segment_end,
1579 .segment_reg = aspeed_spi_segment_reg,
1580 .adjust_window = aspeed_adjust_window_ast2400,
1581 };
1582
1583 static const struct aspeed_spi_data ast2400_spi_data = {
1584 .max_cs = 1,
1585 .hastype = false,
1586 .we0 = 0,
1587 .ctl0 = 0x04,
1588 .timing = 0x14,
1589 .hclk_mask = 0xfffff0ff,
1590 .hdiv_max = 1,
1591 .full_duplex = false,
1592 .get_clk_div = aspeed_get_clk_div_ast2400,
1593 .calibrate = aspeed_spi_calibrate,
1594 /* No segment registers */
1595 };
1596
1597 static const struct aspeed_spi_data ast2500_fmc_data = {
1598 .max_cs = 3,
1599 .hastype = true,
1600 .we0 = 16,
1601 .ctl0 = CE0_CTRL_REG,
1602 .timing = CE0_TIMING_COMPENSATION_REG,
1603 .hclk_mask = 0xffffd0ff,
1604 .hdiv_max = 1,
1605 .min_window_size = 0x800000,
1606 .full_duplex = false,
1607 .get_clk_div = aspeed_get_clk_div_ast2500,
1608 .calibrate = aspeed_spi_calibrate,
1609 .segment_start = aspeed_spi_segment_start,
1610 .segment_end = aspeed_spi_segment_end,
1611 .segment_reg = aspeed_spi_segment_reg,
1612 .adjust_window = aspeed_adjust_window_ast2500,
1613 };
1614
1615 static const struct aspeed_spi_data ast2500_spi_data = {
1616 .max_cs = 2,
1617 .hastype = false,
1618 .we0 = 16,
1619 .ctl0 = CE0_CTRL_REG,
1620 .timing = CE0_TIMING_COMPENSATION_REG,
1621 .hclk_mask = 0xffffd0ff,
1622 .hdiv_max = 1,
1623 .min_window_size = 0x800000,
1624 .full_duplex = false,
1625 .get_clk_div = aspeed_get_clk_div_ast2500,
1626 .calibrate = aspeed_spi_calibrate,
1627 .segment_start = aspeed_spi_segment_start,
1628 .segment_end = aspeed_spi_segment_end,
1629 .segment_reg = aspeed_spi_segment_reg,
1630 .adjust_window = aspeed_adjust_window_ast2500,
1631 };
1632
1633 static const struct aspeed_spi_data ast2600_fmc_data = {
1634 .max_cs = 3,
1635 .hastype = false,
1636 .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD,
1637 .we0 = 16,
1638 .ctl0 = CE0_CTRL_REG,
1639 .timing = CE0_TIMING_COMPENSATION_REG,
1640 .hclk_mask = 0xf0fff0ff,
1641 .hdiv_max = 2,
1642 .min_window_size = 0x200000,
1643 .full_duplex = false,
1644 .get_clk_div = aspeed_get_clk_div_ast2600,
1645 .calibrate = aspeed_spi_ast2600_calibrate,
1646 .segment_start = aspeed_spi_segment_ast2600_start,
1647 .segment_end = aspeed_spi_segment_ast2600_end,
1648 .segment_reg = aspeed_spi_segment_ast2600_reg,
1649 .adjust_window = aspeed_adjust_window_ast2600,
1650 };
1651
1652 static const struct aspeed_spi_data ast2600_spi_data = {
1653 .max_cs = 2,
1654 .hastype = false,
1655 .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD,
1656 .we0 = 16,
1657 .ctl0 = CE0_CTRL_REG,
1658 .timing = CE0_TIMING_COMPENSATION_REG,
1659 .hclk_mask = 0xf0fff0ff,
1660 .hdiv_max = 2,
1661 .min_window_size = 0x200000,
1662 .full_duplex = false,
1663 .get_clk_div = aspeed_get_clk_div_ast2600,
1664 .calibrate = aspeed_spi_ast2600_calibrate,
1665 .segment_start = aspeed_spi_segment_ast2600_start,
1666 .segment_end = aspeed_spi_segment_ast2600_end,
1667 .segment_reg = aspeed_spi_segment_ast2600_reg,
1668 .adjust_window = aspeed_adjust_window_ast2600,
1669 };
1670
1671 static const struct aspeed_spi_data ast2700_fmc_data = {
1672 .max_cs = 3,
1673 .hastype = false,
1674 .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD,
1675 .we0 = 16,
1676 .ctl0 = CE0_CTRL_REG,
1677 .timing = CE0_TIMING_COMPENSATION_REG,
1678 .hclk_mask = 0xf0fff0ff,
1679 .hdiv_max = 2,
1680 .min_window_size = 0x10000,
1681 .full_duplex = true,
1682 .get_clk_div = aspeed_get_clk_div_ast2600,
1683 .calibrate = aspeed_spi_ast2600_calibrate,
1684 .segment_start = aspeed_spi_segment_ast2700_start,
1685 .segment_end = aspeed_spi_segment_ast2700_end,
1686 .segment_reg = aspeed_spi_segment_ast2700_reg,
1687 };
1688
1689 static const struct aspeed_spi_data ast2700_spi_data = {
1690 .max_cs = 2,
1691 .hastype = false,
1692 .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD,
1693 .we0 = 16,
1694 .ctl0 = CE0_CTRL_REG,
1695 .timing = CE0_TIMING_COMPENSATION_REG,
1696 .hclk_mask = 0xf0fff0ff,
1697 .hdiv_max = 2,
1698 .min_window_size = 0x10000,
1699 .full_duplex = true,
1700 .get_clk_div = aspeed_get_clk_div_ast2600,
1701 .calibrate = aspeed_spi_ast2600_calibrate,
1702 .segment_start = aspeed_spi_segment_ast2700_start,
1703 .segment_end = aspeed_spi_segment_ast2700_end,
1704 .segment_reg = aspeed_spi_segment_ast2700_reg,
1705 };
1706
1707 static const struct of_device_id aspeed_spi_matches[] = {
1708 { .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
1709 { .compatible = "aspeed,ast2400-spi", .data = &ast2400_spi_data },
1710 { .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
1711 { .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
1712 { .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
1713 { .compatible = "aspeed,ast2600-spi", .data = &ast2600_spi_data },
1714 { .compatible = "aspeed,ast2700-fmc", .data = &ast2700_fmc_data },
1715 { .compatible = "aspeed,ast2700-spi", .data = &ast2700_spi_data },
1716 { }
1717 };
1718 MODULE_DEVICE_TABLE(of, aspeed_spi_matches);
1719
1720 static struct platform_driver aspeed_spi_driver = {
1721 .probe = aspeed_spi_probe,
1722 .remove = aspeed_spi_remove,
1723 .driver = {
1724 .name = DEVICE_NAME,
1725 .of_match_table = aspeed_spi_matches,
1726 }
1727 };
1728
1729 module_platform_driver(aspeed_spi_driver);
1730
1731 MODULE_DESCRIPTION("ASPEED Static Memory Controller Driver");
1732 MODULE_AUTHOR("Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>");
1733 MODULE_AUTHOR("Cedric Le Goater <clg@kaod.org>");
1734 MODULE_LICENSE("GPL v2");
1735