1 /*
2 * Broadcom BCM63XX High Speed SPI Controller driver
3 *
4 * Copyright 2000-2010 Broadcom Corporation
5 * Copyright 2012-2013 Jonas Gorski <jonas.gorski@gmail.com>
6 *
7 * Licensed under the GNU/GPL. See COPYING for details.
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/io.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/spi/spi.h>
21 #include <linux/mutex.h>
22 #include <linux/of.h>
23 #include <linux/spi/spi-mem.h>
24 #include <linux/mtd/spi-nor.h>
25 #include <linux/reset.h>
26 #include <linux/pm_runtime.h>
27
28 #define HSSPI_GLOBAL_CTRL_REG 0x0
29 #define GLOBAL_CTRL_CS_POLARITY_SHIFT 0
30 #define GLOBAL_CTRL_CS_POLARITY_MASK 0x000000ff
31 #define GLOBAL_CTRL_PLL_CLK_CTRL_SHIFT 8
32 #define GLOBAL_CTRL_PLL_CLK_CTRL_MASK 0x0000ff00
33 #define GLOBAL_CTRL_CLK_GATE_SSOFF BIT(16)
34 #define GLOBAL_CTRL_CLK_POLARITY BIT(17)
35 #define GLOBAL_CTRL_MOSI_IDLE BIT(18)
36
37 #define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4
38
39 #define HSSPI_INT_STATUS_REG 0x8
40 #define HSSPI_INT_STATUS_MASKED_REG 0xc
41 #define HSSPI_INT_MASK_REG 0x10
42
43 #define HSSPI_PINGx_CMD_DONE(i) BIT((i * 8) + 0)
44 #define HSSPI_PINGx_RX_OVER(i) BIT((i * 8) + 1)
45 #define HSSPI_PINGx_TX_UNDER(i) BIT((i * 8) + 2)
46 #define HSSPI_PINGx_POLL_TIMEOUT(i) BIT((i * 8) + 3)
47 #define HSSPI_PINGx_CTRL_INVAL(i) BIT((i * 8) + 4)
48
49 #define HSSPI_INT_CLEAR_ALL 0xff001f1f
50
51 #define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40)
52 #define PINGPONG_CMD_COMMAND_MASK 0xf
53 #define PINGPONG_COMMAND_NOOP 0
54 #define PINGPONG_COMMAND_START_NOW 1
55 #define PINGPONG_COMMAND_START_TRIGGER 2
56 #define PINGPONG_COMMAND_HALT 3
57 #define PINGPONG_COMMAND_FLUSH 4
58 #define PINGPONG_CMD_PROFILE_SHIFT 8
59 #define PINGPONG_CMD_SS_SHIFT 12
60
61 #define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40)
62 #define HSSPI_PINGPONG_STATUS_SRC_BUSY BIT(1)
63
64 #define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20)
65 #define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff
66 #define CLK_CTRL_SPI_CLK_2X_SEL BIT(14)
67 #define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15)
68
69 #define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20)
70 #define SIGNAL_CTRL_LATCH_RISING BIT(12)
71 #define SIGNAL_CTRL_LAUNCH_RISING BIT(13)
72 #define SIGNAL_CTRL_ASYNC_INPUT_PATH BIT(16)
73
74 #define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20)
75 #define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8
76 #define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12
77 #define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16
78 #define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18
79 #define MODE_CTRL_MODE_3WIRE BIT(20)
80 #define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24
81
82 #define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200)
83
84
85 #define HSSPI_OP_MULTIBIT BIT(11)
86 #define HSSPI_OP_CODE_SHIFT 13
87 #define HSSPI_OP_SLEEP (0 << HSSPI_OP_CODE_SHIFT)
88 #define HSSPI_OP_READ_WRITE (1 << HSSPI_OP_CODE_SHIFT)
89 #define HSSPI_OP_WRITE (2 << HSSPI_OP_CODE_SHIFT)
90 #define HSSPI_OP_READ (3 << HSSPI_OP_CODE_SHIFT)
91 #define HSSPI_OP_SETIRQ (4 << HSSPI_OP_CODE_SHIFT)
92
93 #define HSSPI_BUFFER_LEN 512
94 #define HSSPI_OPCODE_LEN 2
95
96 #define HSSPI_MAX_PREPEND_LEN 15
97
98 /*
99 * Some chip require 30MHz but other require 25MHz. Use smaller value to cover
100 * both cases.
101 */
102 #define HSSPI_MAX_SYNC_CLOCK 25000000
103
104 #define HSSPI_SPI_MAX_CS 8
105 #define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
106 #define HSSPI_POLL_STATUS_TIMEOUT_MS 100
107
108 #define HSSPI_WAIT_MODE_POLLING 0
109 #define HSSPI_WAIT_MODE_INTR 1
110 #define HSSPI_WAIT_MODE_MAX HSSPI_WAIT_MODE_INTR
111
112 /*
113 * Default transfer mode is auto. If the msg is prependable, use the prepend
114 * mode. If not, falls back to use the dummy cs workaround mode but limit the
115 * clock to 25MHz to make sure it works in all board design.
116 */
117 #define HSSPI_XFER_MODE_AUTO 0
118 #define HSSPI_XFER_MODE_PREPEND 1
119 #define HSSPI_XFER_MODE_DUMMYCS 2
120 #define HSSPI_XFER_MODE_MAX HSSPI_XFER_MODE_DUMMYCS
121
122 #define bcm63xx_prepend_printk_on_checkfail(bs, fmt, ...) \
123 do { \
124 if (bs->xfer_mode == HSSPI_XFER_MODE_AUTO) \
125 dev_dbg(&bs->pdev->dev, fmt, ##__VA_ARGS__); \
126 else if (bs->xfer_mode == HSSPI_XFER_MODE_PREPEND) \
127 dev_err(&bs->pdev->dev, fmt, ##__VA_ARGS__); \
128 } while (0)
129
130 struct bcm63xx_hsspi {
131 struct completion done;
132 struct mutex bus_mutex;
133 struct mutex msg_mutex;
134 struct platform_device *pdev;
135 struct clk *clk;
136 struct clk *pll_clk;
137 void __iomem *regs;
138 u8 __iomem *fifo;
139
140 u32 speed_hz;
141 u8 cs_polarity;
142 u32 wait_mode;
143 u32 xfer_mode;
144 u32 prepend_cnt;
145 u32 md_start;
146 u8 *prepend_buf;
147 };
148
wait_mode_show(struct device * dev,struct device_attribute * attr,char * buf)149 static ssize_t wait_mode_show(struct device *dev, struct device_attribute *attr,
150 char *buf)
151 {
152 struct spi_controller *ctrl = dev_get_drvdata(dev);
153 struct bcm63xx_hsspi *bs = spi_controller_get_devdata(ctrl);
154
155 return sprintf(buf, "%d\n", bs->wait_mode);
156 }
157
wait_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)158 static ssize_t wait_mode_store(struct device *dev, struct device_attribute *attr,
159 const char *buf, size_t count)
160 {
161 struct spi_controller *ctrl = dev_get_drvdata(dev);
162 struct bcm63xx_hsspi *bs = spi_controller_get_devdata(ctrl);
163 u32 val;
164
165 if (kstrtou32(buf, 10, &val))
166 return -EINVAL;
167
168 if (val > HSSPI_WAIT_MODE_MAX) {
169 dev_warn(dev, "invalid wait mode %u\n", val);
170 return -EINVAL;
171 }
172
173 mutex_lock(&bs->msg_mutex);
174 bs->wait_mode = val;
175 /* clear interrupt status to avoid spurious int on next transfer */
176 if (val == HSSPI_WAIT_MODE_INTR)
177 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
178 mutex_unlock(&bs->msg_mutex);
179
180 return count;
181 }
182
183 static DEVICE_ATTR_RW(wait_mode);
184
xfer_mode_show(struct device * dev,struct device_attribute * attr,char * buf)185 static ssize_t xfer_mode_show(struct device *dev, struct device_attribute *attr,
186 char *buf)
187 {
188 struct spi_controller *ctrl = dev_get_drvdata(dev);
189 struct bcm63xx_hsspi *bs = spi_controller_get_devdata(ctrl);
190
191 return sprintf(buf, "%d\n", bs->xfer_mode);
192 }
193
xfer_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)194 static ssize_t xfer_mode_store(struct device *dev, struct device_attribute *attr,
195 const char *buf, size_t count)
196 {
197 struct spi_controller *ctrl = dev_get_drvdata(dev);
198 struct bcm63xx_hsspi *bs = spi_controller_get_devdata(ctrl);
199 u32 val;
200
201 if (kstrtou32(buf, 10, &val))
202 return -EINVAL;
203
204 if (val > HSSPI_XFER_MODE_MAX) {
205 dev_warn(dev, "invalid xfer mode %u\n", val);
206 return -EINVAL;
207 }
208
209 mutex_lock(&bs->msg_mutex);
210 bs->xfer_mode = val;
211 mutex_unlock(&bs->msg_mutex);
212
213 return count;
214 }
215
216 static DEVICE_ATTR_RW(xfer_mode);
217
218 static struct attribute *bcm63xx_hsspi_attrs[] = {
219 &dev_attr_wait_mode.attr,
220 &dev_attr_xfer_mode.attr,
221 NULL,
222 };
223
224 static const struct attribute_group bcm63xx_hsspi_group = {
225 .attrs = bcm63xx_hsspi_attrs,
226 };
227
228 static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
229 struct spi_device *spi, int hz);
230
bcm63xx_hsspi_max_message_size(struct spi_device * spi)231 static size_t bcm63xx_hsspi_max_message_size(struct spi_device *spi)
232 {
233 return HSSPI_BUFFER_LEN - HSSPI_OPCODE_LEN;
234 }
235
bcm63xx_hsspi_wait_cmd(struct bcm63xx_hsspi * bs)236 static int bcm63xx_hsspi_wait_cmd(struct bcm63xx_hsspi *bs)
237 {
238 unsigned long limit;
239 u32 reg = 0;
240 int rc = 0;
241
242 if (bs->wait_mode == HSSPI_WAIT_MODE_INTR) {
243 if (wait_for_completion_timeout(&bs->done, HZ) == 0)
244 rc = 1;
245 } else {
246 /* polling mode checks for status busy bit */
247 limit = jiffies + msecs_to_jiffies(HSSPI_POLL_STATUS_TIMEOUT_MS);
248
249 while (!time_after(jiffies, limit)) {
250 reg = __raw_readl(bs->regs + HSSPI_PINGPONG_STATUS_REG(0));
251 if (reg & HSSPI_PINGPONG_STATUS_SRC_BUSY)
252 cpu_relax();
253 else
254 break;
255 }
256 if (reg & HSSPI_PINGPONG_STATUS_SRC_BUSY)
257 rc = 1;
258 }
259
260 if (rc)
261 dev_err(&bs->pdev->dev, "transfer timed out!\n");
262
263 return rc;
264 }
265
bcm63xx_prepare_prepend_transfer(struct spi_controller * host,struct spi_message * msg,struct spi_transfer * t_prepend)266 static bool bcm63xx_prepare_prepend_transfer(struct spi_controller *host,
267 struct spi_message *msg,
268 struct spi_transfer *t_prepend)
269 {
270
271 struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host);
272 bool tx_only = false, multidata = false;
273 struct spi_transfer *t;
274
275 /*
276 * Multiple transfers within a message may be combined into one transfer
277 * to the controller using its prepend feature. A SPI message is prependable
278 * only if the following are all true:
279 * 1. One or more half duplex write transfers at the start
280 * 2. Optional switch from single to dual bit within the write transfers
281 * 3. Optional full duplex read/write at the end if all single bit
282 * 4. No delay and cs_change between transfers
283 */
284 bs->prepend_cnt = 0;
285 bs->md_start = 0;
286 list_for_each_entry(t, &msg->transfers, transfer_list) {
287 if ((spi_delay_to_ns(&t->delay, t) > 0) || t->cs_change) {
288 bcm63xx_prepend_printk_on_checkfail(bs,
289 "Delay or cs change not supported in prepend mode!\n");
290 return false;
291 }
292
293 tx_only = false;
294 if (t->tx_buf && !t->rx_buf) {
295 tx_only = true;
296 if (bs->prepend_cnt + t->len >
297 (HSSPI_BUFFER_LEN - HSSPI_OPCODE_LEN)) {
298 bcm63xx_prepend_printk_on_checkfail(bs,
299 "exceed max buf len, abort prepending transfers!\n");
300 return false;
301 }
302
303 if (t->tx_nbits == SPI_NBITS_SINGLE &&
304 !list_is_last(&t->transfer_list, &msg->transfers) &&
305 multidata) {
306 bcm63xx_prepend_printk_on_checkfail(bs,
307 "single-bit after multi-bit not supported!\n");
308 return false;
309 }
310
311 if (t->tx_nbits > SPI_NBITS_SINGLE)
312 multidata = true;
313
314 memcpy(bs->prepend_buf + bs->prepend_cnt, t->tx_buf, t->len);
315 bs->prepend_cnt += t->len;
316
317 if (t->tx_nbits == SPI_NBITS_SINGLE)
318 bs->md_start += t->len;
319
320 } else {
321 if (!list_is_last(&t->transfer_list, &msg->transfers)) {
322 bcm63xx_prepend_printk_on_checkfail(bs,
323 "rx/tx_rx transfer not supported when it is not last one!\n");
324 return false;
325 }
326
327 if (t->rx_buf && t->rx_nbits == SPI_NBITS_SINGLE &&
328 multidata) {
329 bcm63xx_prepend_printk_on_checkfail(bs,
330 "single-bit after multi-bit not supported!\n");
331 return false;
332 }
333 }
334
335 if (list_is_last(&t->transfer_list, &msg->transfers)) {
336 memcpy(t_prepend, t, sizeof(struct spi_transfer));
337
338 if (tx_only) {
339 /*
340 * if the last one is also a tx only transfer, merge
341 * all of them into one single tx transfer
342 */
343 t_prepend->len = bs->prepend_cnt;
344 t_prepend->tx_buf = bs->prepend_buf;
345 bs->prepend_cnt = 0;
346 } else {
347 /*
348 * if the last one is not a tx only transfer, all
349 * the previous transfers are sent through prepend bytes and
350 * make sure it does not exceed the max prepend len
351 */
352 if (bs->prepend_cnt > HSSPI_MAX_PREPEND_LEN) {
353 bcm63xx_prepend_printk_on_checkfail(bs,
354 "exceed max prepend len, abort prepending transfers!\n");
355 return false;
356 }
357 }
358 /*
359 * If switching from single-bit to multi-bit, make sure
360 * the start offset does not exceed the maximum
361 */
362 if (multidata && bs->md_start > HSSPI_MAX_PREPEND_LEN) {
363 bcm63xx_prepend_printk_on_checkfail(bs,
364 "exceed max multi-bit offset, abort prepending transfers!\n");
365 return false;
366 }
367 }
368 }
369
370 return true;
371 }
372
bcm63xx_hsspi_do_prepend_txrx(struct spi_device * spi,struct spi_transfer * t)373 static int bcm63xx_hsspi_do_prepend_txrx(struct spi_device *spi,
374 struct spi_transfer *t)
375 {
376 struct bcm63xx_hsspi *bs = spi_controller_get_devdata(spi->controller);
377 unsigned int chip_select = spi_get_chipselect(spi, 0);
378 u16 opcode = 0, val;
379 const u8 *tx = t->tx_buf;
380 u8 *rx = t->rx_buf;
381 u32 reg = 0;
382
383 /*
384 * shouldn't happen as we set the max_message_size in the probe.
385 * but check it again in case some driver does not honor the max size
386 */
387 if (t->len + bs->prepend_cnt > (HSSPI_BUFFER_LEN - HSSPI_OPCODE_LEN)) {
388 dev_warn(&bs->pdev->dev,
389 "Prepend message large than fifo size len %d prepend %d\n",
390 t->len, bs->prepend_cnt);
391 return -EINVAL;
392 }
393
394 bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
395
396 if (tx && rx)
397 opcode = HSSPI_OP_READ_WRITE;
398 else if (tx)
399 opcode = HSSPI_OP_WRITE;
400 else if (rx)
401 opcode = HSSPI_OP_READ;
402
403 if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
404 (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) {
405 opcode |= HSSPI_OP_MULTIBIT;
406
407 if (t->rx_nbits == SPI_NBITS_DUAL) {
408 reg |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT;
409 reg |= bs->md_start << MODE_CTRL_MULTIDATA_RD_STRT_SHIFT;
410 }
411 if (t->tx_nbits == SPI_NBITS_DUAL) {
412 reg |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT;
413 reg |= bs->md_start << MODE_CTRL_MULTIDATA_WR_STRT_SHIFT;
414 }
415 }
416
417 reg |= bs->prepend_cnt << MODE_CTRL_PREPENDBYTE_CNT_SHIFT;
418 __raw_writel(reg | 0xff,
419 bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
420
421 reinit_completion(&bs->done);
422 if (bs->prepend_cnt)
423 memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, bs->prepend_buf,
424 bs->prepend_cnt);
425 if (tx)
426 memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN + bs->prepend_cnt, tx,
427 t->len);
428
429 *(__be16 *)(&val) = cpu_to_be16(opcode | t->len);
430 __raw_writew(val, bs->fifo);
431 /* enable interrupt */
432 if (bs->wait_mode == HSSPI_WAIT_MODE_INTR)
433 __raw_writel(HSSPI_PINGx_CMD_DONE(0), bs->regs + HSSPI_INT_MASK_REG);
434
435 /* start the transfer */
436 reg = chip_select << PINGPONG_CMD_SS_SHIFT |
437 chip_select << PINGPONG_CMD_PROFILE_SHIFT |
438 PINGPONG_COMMAND_START_NOW;
439 __raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
440
441 if (bcm63xx_hsspi_wait_cmd(bs))
442 return -ETIMEDOUT;
443
444 if (rx)
445 memcpy_fromio(rx, bs->fifo, t->len);
446
447 return 0;
448 }
449
bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi * bs,unsigned int cs,bool active)450 static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs,
451 bool active)
452 {
453 u32 reg;
454
455 mutex_lock(&bs->bus_mutex);
456 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
457
458 reg &= ~BIT(cs);
459 if (active == !(bs->cs_polarity & BIT(cs)))
460 reg |= BIT(cs);
461
462 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
463 mutex_unlock(&bs->bus_mutex);
464 }
465
bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi * bs,struct spi_device * spi,int hz)466 static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
467 struct spi_device *spi, int hz)
468 {
469 unsigned int profile = spi_get_chipselect(spi, 0);
470 u32 reg;
471
472 reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz));
473 __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg,
474 bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile));
475
476 reg = __raw_readl(bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
477 if (hz > HSSPI_MAX_SYNC_CLOCK)
478 reg |= SIGNAL_CTRL_ASYNC_INPUT_PATH;
479 else
480 reg &= ~SIGNAL_CTRL_ASYNC_INPUT_PATH;
481 __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile));
482
483 mutex_lock(&bs->bus_mutex);
484 /* setup clock polarity */
485 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
486 reg &= ~GLOBAL_CTRL_CLK_POLARITY;
487 if (spi->mode & SPI_CPOL)
488 reg |= GLOBAL_CTRL_CLK_POLARITY;
489 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
490 mutex_unlock(&bs->bus_mutex);
491 }
492
bcm63xx_hsspi_do_txrx(struct spi_device * spi,struct spi_transfer * t)493 static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
494 {
495 struct bcm63xx_hsspi *bs = spi_controller_get_devdata(spi->controller);
496 unsigned int chip_select = spi_get_chipselect(spi, 0);
497 u16 opcode = 0, val;
498 int pending = t->len;
499 int step_size = HSSPI_BUFFER_LEN;
500 const u8 *tx = t->tx_buf;
501 u8 *rx = t->rx_buf;
502 u32 reg = 0;
503
504 bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz);
505 if (!t->cs_off)
506 bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), true);
507
508 if (tx && rx)
509 opcode = HSSPI_OP_READ_WRITE;
510 else if (tx)
511 opcode = HSSPI_OP_WRITE;
512 else if (rx)
513 opcode = HSSPI_OP_READ;
514
515 if (opcode != HSSPI_OP_READ)
516 step_size -= HSSPI_OPCODE_LEN;
517
518 if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) ||
519 (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) {
520 opcode |= HSSPI_OP_MULTIBIT;
521
522 if (t->rx_nbits == SPI_NBITS_DUAL)
523 reg |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT;
524 if (t->tx_nbits == SPI_NBITS_DUAL)
525 reg |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT;
526 }
527
528 __raw_writel(reg | 0xff,
529 bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select));
530
531 while (pending > 0) {
532 int curr_step = min_t(int, step_size, pending);
533
534 reinit_completion(&bs->done);
535 if (tx) {
536 memcpy_toio(bs->fifo + HSSPI_OPCODE_LEN, tx, curr_step);
537 tx += curr_step;
538 }
539
540 *(__be16 *)(&val) = cpu_to_be16(opcode | curr_step);
541 __raw_writew(val, bs->fifo);
542
543 /* enable interrupt */
544 if (bs->wait_mode == HSSPI_WAIT_MODE_INTR)
545 __raw_writel(HSSPI_PINGx_CMD_DONE(0),
546 bs->regs + HSSPI_INT_MASK_REG);
547
548 reg = !chip_select << PINGPONG_CMD_SS_SHIFT |
549 chip_select << PINGPONG_CMD_PROFILE_SHIFT |
550 PINGPONG_COMMAND_START_NOW;
551 __raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0));
552
553 if (bcm63xx_hsspi_wait_cmd(bs))
554 return -ETIMEDOUT;
555
556 if (rx) {
557 memcpy_fromio(rx, bs->fifo, curr_step);
558 rx += curr_step;
559 }
560
561 pending -= curr_step;
562 }
563
564 return 0;
565 }
566
bcm63xx_hsspi_setup(struct spi_device * spi)567 static int bcm63xx_hsspi_setup(struct spi_device *spi)
568 {
569 struct bcm63xx_hsspi *bs = spi_controller_get_devdata(spi->controller);
570 u32 reg;
571
572 reg = __raw_readl(bs->regs +
573 HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0)));
574 reg &= ~(SIGNAL_CTRL_LAUNCH_RISING | SIGNAL_CTRL_LATCH_RISING);
575 if (spi->mode & SPI_CPHA)
576 reg |= SIGNAL_CTRL_LAUNCH_RISING;
577 else
578 reg |= SIGNAL_CTRL_LATCH_RISING;
579 __raw_writel(reg, bs->regs +
580 HSSPI_PROFILE_SIGNAL_CTRL_REG(spi_get_chipselect(spi, 0)));
581
582 mutex_lock(&bs->bus_mutex);
583 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
584
585 /* only change actual polarities if there is no transfer */
586 if ((reg & GLOBAL_CTRL_CS_POLARITY_MASK) == bs->cs_polarity) {
587 if (spi->mode & SPI_CS_HIGH)
588 reg |= BIT(spi_get_chipselect(spi, 0));
589 else
590 reg &= ~BIT(spi_get_chipselect(spi, 0));
591 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG);
592 }
593
594 if (spi->mode & SPI_CS_HIGH)
595 bs->cs_polarity |= BIT(spi_get_chipselect(spi, 0));
596 else
597 bs->cs_polarity &= ~BIT(spi_get_chipselect(spi, 0));
598
599 mutex_unlock(&bs->bus_mutex);
600
601 return 0;
602 }
603
bcm63xx_hsspi_do_dummy_cs_txrx(struct spi_device * spi,struct spi_message * msg)604 static int bcm63xx_hsspi_do_dummy_cs_txrx(struct spi_device *spi,
605 struct spi_message *msg)
606 {
607 struct bcm63xx_hsspi *bs = spi_controller_get_devdata(spi->controller);
608 int status = -EINVAL;
609 int dummy_cs;
610 bool keep_cs = false;
611 struct spi_transfer *t;
612
613 /*
614 * This controller does not support keeping CS active during idle.
615 * To work around this, we use the following ugly hack:
616 *
617 * a. Invert the target chip select's polarity so it will be active.
618 * b. Select a "dummy" chip select to use as the hardware target.
619 * c. Invert the dummy chip select's polarity so it will be inactive
620 * during the actual transfers.
621 * d. Tell the hardware to send to the dummy chip select. Thanks to
622 * the multiplexed nature of SPI the actual target will receive
623 * the transfer and we see its response.
624 *
625 * e. At the end restore the polarities again to their default values.
626 */
627
628 dummy_cs = !spi_get_chipselect(spi, 0);
629 bcm63xx_hsspi_set_cs(bs, dummy_cs, true);
630
631 list_for_each_entry(t, &msg->transfers, transfer_list) {
632 /*
633 * We are here because one of reasons below:
634 * a. Message is not prependable and in default auto xfer mode. This mean
635 * we fallback to dummy cs mode at maximum 25MHz safe clock rate.
636 * b. User set to use the dummy cs mode.
637 */
638 if (bs->xfer_mode == HSSPI_XFER_MODE_AUTO) {
639 if (t->speed_hz > HSSPI_MAX_SYNC_CLOCK) {
640 t->speed_hz = HSSPI_MAX_SYNC_CLOCK;
641 dev_warn_once(&bs->pdev->dev,
642 "Force to dummy cs mode. Reduce the speed to %dHz",
643 t->speed_hz);
644 }
645 }
646
647 status = bcm63xx_hsspi_do_txrx(spi, t);
648 if (status)
649 break;
650
651 msg->actual_length += t->len;
652
653 spi_transfer_delay_exec(t);
654
655 /* use existing cs change logic from spi_transfer_one_message */
656 if (t->cs_change) {
657 if (list_is_last(&t->transfer_list, &msg->transfers)) {
658 keep_cs = true;
659 } else {
660 if (!t->cs_off)
661 bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);
662
663 spi_transfer_cs_change_delay_exec(msg, t);
664
665 if (!list_next_entry(t, transfer_list)->cs_off)
666 bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), true);
667 }
668 } else if (!list_is_last(&t->transfer_list, &msg->transfers) &&
669 t->cs_off != list_next_entry(t, transfer_list)->cs_off) {
670 bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), t->cs_off);
671 }
672 }
673
674 bcm63xx_hsspi_set_cs(bs, dummy_cs, false);
675 if (status || !keep_cs)
676 bcm63xx_hsspi_set_cs(bs, spi_get_chipselect(spi, 0), false);
677
678 return status;
679 }
680
bcm63xx_hsspi_transfer_one(struct spi_controller * host,struct spi_message * msg)681 static int bcm63xx_hsspi_transfer_one(struct spi_controller *host,
682 struct spi_message *msg)
683 {
684 struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host);
685 struct spi_device *spi = msg->spi;
686 int status = -EINVAL;
687 bool prependable = false;
688 struct spi_transfer t_prepend;
689
690 mutex_lock(&bs->msg_mutex);
691
692 if (bs->xfer_mode != HSSPI_XFER_MODE_DUMMYCS)
693 prependable = bcm63xx_prepare_prepend_transfer(host, msg, &t_prepend);
694
695 if (prependable) {
696 status = bcm63xx_hsspi_do_prepend_txrx(spi, &t_prepend);
697 msg->actual_length = (t_prepend.len + bs->prepend_cnt);
698 } else {
699 if (bs->xfer_mode == HSSPI_XFER_MODE_PREPEND) {
700 dev_err(&bs->pdev->dev,
701 "User sets prepend mode but msg not prependable! Abort transfer\n");
702 status = -EINVAL;
703 } else
704 status = bcm63xx_hsspi_do_dummy_cs_txrx(spi, msg);
705 }
706
707 mutex_unlock(&bs->msg_mutex);
708 msg->status = status;
709 spi_finalize_current_message(host);
710
711 return 0;
712 }
713
bcm63xx_hsspi_mem_supports_op(struct spi_mem * mem,const struct spi_mem_op * op)714 static bool bcm63xx_hsspi_mem_supports_op(struct spi_mem *mem,
715 const struct spi_mem_op *op)
716 {
717 if (!spi_mem_default_supports_op(mem, op))
718 return false;
719
720 return true;
721 }
722
723 static const struct spi_controller_mem_ops bcm63xx_hsspi_mem_ops = {
724 .supports_op = bcm63xx_hsspi_mem_supports_op,
725 };
726
bcm63xx_hsspi_interrupt(int irq,void * dev_id)727 static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
728 {
729 struct bcm63xx_hsspi *bs = (struct bcm63xx_hsspi *)dev_id;
730
731 if (__raw_readl(bs->regs + HSSPI_INT_STATUS_MASKED_REG) == 0)
732 return IRQ_NONE;
733
734 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
735 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
736
737 complete(&bs->done);
738
739 return IRQ_HANDLED;
740 }
741
bcm63xx_hsspi_probe(struct platform_device * pdev)742 static int bcm63xx_hsspi_probe(struct platform_device *pdev)
743 {
744 struct spi_controller *host;
745 struct bcm63xx_hsspi *bs;
746 void __iomem *regs;
747 struct device *dev = &pdev->dev;
748 struct clk *clk, *pll_clk = NULL;
749 int irq, ret;
750 u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS;
751 struct reset_control *reset;
752
753 irq = platform_get_irq(pdev, 0);
754 if (irq < 0)
755 return irq;
756
757 regs = devm_platform_ioremap_resource(pdev, 0);
758 if (IS_ERR(regs))
759 return PTR_ERR(regs);
760
761 clk = devm_clk_get_enabled(dev, "hsspi");
762 if (IS_ERR(clk))
763 return PTR_ERR(clk);
764
765 reset = devm_reset_control_get_optional_shared(dev, NULL);
766 if (IS_ERR(reset))
767 return PTR_ERR(reset);
768
769 ret = reset_control_reset(reset);
770 if (ret)
771 return dev_err_probe(dev, ret, "unable to reset device: %d\n", ret);
772
773 rate = clk_get_rate(clk);
774 if (!rate) {
775 pll_clk = devm_clk_get_enabled(dev, "pll");
776 if (IS_ERR(pll_clk))
777 return dev_err_probe(dev, PTR_ERR(pll_clk),
778 "failed enable pll clk\n");
779
780 rate = clk_get_rate(pll_clk);
781 if (!rate)
782 return dev_err_probe(dev, -EINVAL,
783 "failed get pll clk rate\n");
784 }
785
786 host = spi_alloc_host(&pdev->dev, sizeof(*bs));
787 if (!host)
788 return dev_err_probe(dev, -ENOMEM, "alloc host no mem\n");
789
790 bs = spi_controller_get_devdata(host);
791 bs->pdev = pdev;
792 bs->clk = clk;
793 bs->pll_clk = pll_clk;
794 bs->regs = regs;
795 bs->speed_hz = rate;
796 bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0));
797 bs->wait_mode = HSSPI_WAIT_MODE_POLLING;
798 bs->prepend_buf = devm_kzalloc(dev, HSSPI_BUFFER_LEN, GFP_KERNEL);
799 if (!bs->prepend_buf) {
800 ret = -ENOMEM;
801 goto out_put_host;
802 }
803
804 mutex_init(&bs->bus_mutex);
805 mutex_init(&bs->msg_mutex);
806 init_completion(&bs->done);
807
808 host->mem_ops = &bcm63xx_hsspi_mem_ops;
809 if (!dev->of_node)
810 host->bus_num = HSSPI_BUS_NUM;
811
812 of_property_read_u32(dev->of_node, "num-cs", &num_cs);
813 if (num_cs > 8) {
814 dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
815 num_cs);
816 num_cs = HSSPI_SPI_MAX_CS;
817 }
818 host->num_chipselect = num_cs;
819 host->setup = bcm63xx_hsspi_setup;
820 host->transfer_one_message = bcm63xx_hsspi_transfer_one;
821 host->max_transfer_size = bcm63xx_hsspi_max_message_size;
822 host->max_message_size = bcm63xx_hsspi_max_message_size;
823
824 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
825 SPI_RX_DUAL | SPI_TX_DUAL;
826 host->bits_per_word_mask = SPI_BPW_MASK(8);
827 host->auto_runtime_pm = true;
828
829 platform_set_drvdata(pdev, host);
830
831 /* Initialize the hardware */
832 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
833
834 /* clean up any pending interrupts */
835 __raw_writel(HSSPI_INT_CLEAR_ALL, bs->regs + HSSPI_INT_STATUS_REG);
836
837 /* read out default CS polarities */
838 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG);
839 bs->cs_polarity = reg & GLOBAL_CTRL_CS_POLARITY_MASK;
840 __raw_writel(reg | GLOBAL_CTRL_CLK_GATE_SSOFF,
841 bs->regs + HSSPI_GLOBAL_CTRL_REG);
842
843 if (irq > 0) {
844 ret = devm_request_irq(dev, irq, bcm63xx_hsspi_interrupt, IRQF_SHARED,
845 pdev->name, bs);
846
847 if (ret)
848 goto out_put_host;
849 }
850
851 pm_runtime_enable(&pdev->dev);
852
853 ret = sysfs_create_group(&pdev->dev.kobj, &bcm63xx_hsspi_group);
854 if (ret) {
855 dev_err(&pdev->dev, "couldn't register sysfs group\n");
856 goto out_pm_disable;
857 }
858
859 /* register and we are done */
860 ret = spi_register_controller(host);
861 if (ret)
862 goto out_sysgroup_disable;
863
864 dev_info(dev, "Broadcom 63XX High Speed SPI Controller driver");
865
866 return 0;
867
868 out_sysgroup_disable:
869 sysfs_remove_group(&pdev->dev.kobj, &bcm63xx_hsspi_group);
870 out_pm_disable:
871 pm_runtime_disable(&pdev->dev);
872 out_put_host:
873 spi_controller_put(host);
874 return ret;
875 }
876
877
bcm63xx_hsspi_remove(struct platform_device * pdev)878 static void bcm63xx_hsspi_remove(struct platform_device *pdev)
879 {
880 struct spi_controller *host = platform_get_drvdata(pdev);
881 struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host);
882
883 spi_controller_get(host);
884
885 spi_unregister_controller(host);
886
887 /* reset the hardware and block queue progress */
888 __raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
889 sysfs_remove_group(&pdev->dev.kobj, &bcm63xx_hsspi_group);
890
891 spi_controller_put(host);
892 }
893
894 #ifdef CONFIG_PM_SLEEP
bcm63xx_hsspi_suspend(struct device * dev)895 static int bcm63xx_hsspi_suspend(struct device *dev)
896 {
897 struct spi_controller *host = dev_get_drvdata(dev);
898 struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host);
899
900 spi_controller_suspend(host);
901 clk_disable_unprepare(bs->pll_clk);
902 clk_disable_unprepare(bs->clk);
903
904 return 0;
905 }
906
bcm63xx_hsspi_resume(struct device * dev)907 static int bcm63xx_hsspi_resume(struct device *dev)
908 {
909 struct spi_controller *host = dev_get_drvdata(dev);
910 struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host);
911 int ret;
912
913 ret = clk_prepare_enable(bs->clk);
914 if (ret)
915 return ret;
916
917 if (bs->pll_clk) {
918 ret = clk_prepare_enable(bs->pll_clk);
919 if (ret) {
920 clk_disable_unprepare(bs->clk);
921 return ret;
922 }
923 }
924
925 spi_controller_resume(host);
926
927 return 0;
928 }
929 #endif
930
931 static SIMPLE_DEV_PM_OPS(bcm63xx_hsspi_pm_ops, bcm63xx_hsspi_suspend,
932 bcm63xx_hsspi_resume);
933
934 static const struct of_device_id bcm63xx_hsspi_of_match[] = {
935 { .compatible = "brcm,bcm6328-hsspi", },
936 { .compatible = "brcm,bcmbca-hsspi-v1.0", },
937 { },
938 };
939 MODULE_DEVICE_TABLE(of, bcm63xx_hsspi_of_match);
940
941 static struct platform_driver bcm63xx_hsspi_driver = {
942 .driver = {
943 .name = "bcm63xx-hsspi",
944 .pm = &bcm63xx_hsspi_pm_ops,
945 .of_match_table = bcm63xx_hsspi_of_match,
946 },
947 .probe = bcm63xx_hsspi_probe,
948 .remove = bcm63xx_hsspi_remove,
949 };
950
951 module_platform_driver(bcm63xx_hsspi_driver);
952
953 MODULE_ALIAS("platform:bcm63xx_hsspi");
954 MODULE_DESCRIPTION("Broadcom BCM63xx High Speed SPI Controller driver");
955 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
956 MODULE_LICENSE("GPL");
957