1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // HiSilicon SPI Controller Driver for Kunpeng SoCs
4 //
5 // Copyright (c) 2021 HiSilicon Technologies Co., Ltd.
6 // Author: Jay Fang <f.fangjian@huawei.com>
7 //
8 // This code is based on spi-dw-core.c.
9
10 #include <linux/acpi.h>
11 #include <linux/bitfield.h>
12 #include <linux/debugfs.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/module.h>
17 #include <linux/property.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/spi/spi.h>
21
22 /* Register offsets */
23 #define HISI_SPI_CSCR 0x00 /* cs control register */
24 #define HISI_SPI_CR 0x04 /* spi common control register */
25 #define HISI_SPI_ENR 0x08 /* spi enable register */
26 #define HISI_SPI_FIFOC 0x0c /* fifo level control register */
27 #define HISI_SPI_IMR 0x10 /* interrupt mask register */
28 #define HISI_SPI_DIN 0x14 /* data in register */
29 #define HISI_SPI_DOUT 0x18 /* data out register */
30 #define HISI_SPI_SR 0x1c /* status register */
31 #define HISI_SPI_RISR 0x20 /* raw interrupt status register */
32 #define HISI_SPI_ISR 0x24 /* interrupt status register */
33 #define HISI_SPI_ICR 0x28 /* interrupt clear register */
34 #define HISI_SPI_VERSION 0xe0 /* version register */
35
36 /* Bit fields in HISI_SPI_CR */
37 #define CR_LOOP_MASK GENMASK(1, 1)
38 #define CR_CPOL_MASK GENMASK(2, 2)
39 #define CR_CPHA_MASK GENMASK(3, 3)
40 #define CR_DIV_PRE_MASK GENMASK(11, 4)
41 #define CR_DIV_POST_MASK GENMASK(19, 12)
42 #define CR_BPW_MASK GENMASK(24, 20)
43 #define CR_SPD_MODE_MASK GENMASK(25, 25)
44
45 /* Bit fields in HISI_SPI_FIFOC */
46 #define FIFOC_TX_MASK GENMASK(5, 3)
47 #define FIFOC_RX_MASK GENMASK(11, 9)
48
49 /* Bit fields in HISI_SPI_IMR, 4 bits */
50 #define IMR_RXOF BIT(0) /* Receive Overflow */
51 #define IMR_RXTO BIT(1) /* Receive Timeout */
52 #define IMR_RX BIT(2) /* Receive */
53 #define IMR_TX BIT(3) /* Transmit */
54 #define IMR_MASK (IMR_RXOF | IMR_RXTO | IMR_RX | IMR_TX)
55
56 /* Bit fields in HISI_SPI_SR, 5 bits */
57 #define SR_TXE BIT(0) /* Transmit FIFO empty */
58 #define SR_TXNF BIT(1) /* Transmit FIFO not full */
59 #define SR_RXNE BIT(2) /* Receive FIFO not empty */
60 #define SR_RXF BIT(3) /* Receive FIFO full */
61 #define SR_BUSY BIT(4) /* Busy Flag */
62
63 /* Bit fields in HISI_SPI_ISR, 4 bits */
64 #define ISR_RXOF BIT(0) /* Receive Overflow */
65 #define ISR_RXTO BIT(1) /* Receive Timeout */
66 #define ISR_RX BIT(2) /* Receive */
67 #define ISR_TX BIT(3) /* Transmit */
68 #define ISR_MASK (ISR_RXOF | ISR_RXTO | ISR_RX | ISR_TX)
69
70 /* Bit fields in HISI_SPI_ICR, 2 bits */
71 #define ICR_RXOF BIT(0) /* Receive Overflow */
72 #define ICR_RXTO BIT(1) /* Receive Timeout */
73 #define ICR_MASK (ICR_RXOF | ICR_RXTO)
74
75 #define DIV_POST_MAX 0xFF
76 #define DIV_POST_MIN 0x00
77 #define DIV_PRE_MAX 0xFE
78 #define DIV_PRE_MIN 0x02
79 #define CLK_DIV_MAX ((1 + DIV_POST_MAX) * DIV_PRE_MAX)
80 #define CLK_DIV_MIN ((1 + DIV_POST_MIN) * DIV_PRE_MIN)
81
82 #define DEFAULT_NUM_CS 1
83
84 #define HISI_SPI_WAIT_TIMEOUT_MS 10UL
85
86 enum hisi_spi_rx_level_trig {
87 HISI_SPI_RX_1,
88 HISI_SPI_RX_4,
89 HISI_SPI_RX_8,
90 HISI_SPI_RX_16,
91 HISI_SPI_RX_32,
92 HISI_SPI_RX_64,
93 HISI_SPI_RX_128
94 };
95
96 enum hisi_spi_tx_level_trig {
97 HISI_SPI_TX_1_OR_LESS,
98 HISI_SPI_TX_4_OR_LESS,
99 HISI_SPI_TX_8_OR_LESS,
100 HISI_SPI_TX_16_OR_LESS,
101 HISI_SPI_TX_32_OR_LESS,
102 HISI_SPI_TX_64_OR_LESS,
103 HISI_SPI_TX_128_OR_LESS
104 };
105
106 enum hisi_spi_frame_n_bytes {
107 HISI_SPI_N_BYTES_NULL,
108 HISI_SPI_N_BYTES_U8,
109 HISI_SPI_N_BYTES_U16,
110 HISI_SPI_N_BYTES_U32 = 4
111 };
112
113 /* Slave spi_dev related */
114 struct hisi_chip_data {
115 u32 cr;
116 u32 speed_hz; /* baud rate */
117 u16 clk_div; /* baud rate divider */
118
119 /* clk_div = (1 + div_post) * div_pre */
120 u8 div_post; /* value from 0 to 255 */
121 u8 div_pre; /* value from 2 to 254 (even only!) */
122 };
123
124 struct hisi_spi {
125 struct device *dev;
126
127 void __iomem *regs;
128 int irq;
129 u32 fifo_len; /* depth of the FIFO buffer */
130
131 /* Current message transfer state info */
132 const void *tx;
133 unsigned int tx_len;
134 void *rx;
135 unsigned int rx_len;
136 u8 n_bytes; /* current is a 1/2/4 bytes op */
137
138 struct dentry *debugfs;
139 struct debugfs_regset32 regset;
140 };
141
142 #define HISI_SPI_DBGFS_REG(_name, _off) \
143 { \
144 .name = _name, \
145 .offset = _off, \
146 }
147
148 static const struct debugfs_reg32 hisi_spi_regs[] = {
149 HISI_SPI_DBGFS_REG("CSCR", HISI_SPI_CSCR),
150 HISI_SPI_DBGFS_REG("CR", HISI_SPI_CR),
151 HISI_SPI_DBGFS_REG("ENR", HISI_SPI_ENR),
152 HISI_SPI_DBGFS_REG("FIFOC", HISI_SPI_FIFOC),
153 HISI_SPI_DBGFS_REG("IMR", HISI_SPI_IMR),
154 HISI_SPI_DBGFS_REG("SR", HISI_SPI_SR),
155 HISI_SPI_DBGFS_REG("RISR", HISI_SPI_RISR),
156 HISI_SPI_DBGFS_REG("ISR", HISI_SPI_ISR),
157 HISI_SPI_DBGFS_REG("ICR", HISI_SPI_ICR),
158 HISI_SPI_DBGFS_REG("VERSION", HISI_SPI_VERSION),
159 };
160
hisi_spi_debugfs_init(struct hisi_spi * hs)161 static int hisi_spi_debugfs_init(struct hisi_spi *hs)
162 {
163 char name[32];
164 struct spi_controller *host = dev_get_drvdata(hs->dev);
165
166 snprintf(name, 32, "hisi_spi%d", host->bus_num);
167 hs->debugfs = debugfs_create_dir(name, NULL);
168 if (IS_ERR(hs->debugfs))
169 return -ENOMEM;
170
171 hs->regset.regs = hisi_spi_regs;
172 hs->regset.nregs = ARRAY_SIZE(hisi_spi_regs);
173 hs->regset.base = hs->regs;
174 debugfs_create_regset32("registers", 0400, hs->debugfs, &hs->regset);
175
176 return 0;
177 }
178
hisi_spi_busy(struct hisi_spi * hs)179 static u32 hisi_spi_busy(struct hisi_spi *hs)
180 {
181 return readl(hs->regs + HISI_SPI_SR) & SR_BUSY;
182 }
183
hisi_spi_rx_not_empty(struct hisi_spi * hs)184 static u32 hisi_spi_rx_not_empty(struct hisi_spi *hs)
185 {
186 return readl(hs->regs + HISI_SPI_SR) & SR_RXNE;
187 }
188
hisi_spi_tx_not_full(struct hisi_spi * hs)189 static u32 hisi_spi_tx_not_full(struct hisi_spi *hs)
190 {
191 return readl(hs->regs + HISI_SPI_SR) & SR_TXNF;
192 }
193
hisi_spi_flush_fifo(struct hisi_spi * hs)194 static void hisi_spi_flush_fifo(struct hisi_spi *hs)
195 {
196 unsigned long limit = loops_per_jiffy << 1;
197
198 do {
199 unsigned long inner_limit = loops_per_jiffy;
200
201 while (hisi_spi_rx_not_empty(hs) && --inner_limit) {
202 readl(hs->regs + HISI_SPI_DOUT);
203 cpu_relax();
204 }
205
206 if (!inner_limit) {
207 dev_warn_ratelimited(hs->dev, "RX FIFO flush timeout\n");
208 break;
209 }
210
211 } while (hisi_spi_busy(hs) && --limit);
212
213 if (!limit)
214 dev_warn_ratelimited(hs->dev, "SPI busy timeout\n");
215 }
216
217 /* Disable the controller and all interrupts */
hisi_spi_disable(struct hisi_spi * hs)218 static void hisi_spi_disable(struct hisi_spi *hs)
219 {
220 writel(0, hs->regs + HISI_SPI_ENR);
221 writel(IMR_MASK, hs->regs + HISI_SPI_IMR);
222 writel(ICR_MASK, hs->regs + HISI_SPI_ICR);
223 }
224
hisi_spi_n_bytes(struct spi_transfer * transfer)225 static u8 hisi_spi_n_bytes(struct spi_transfer *transfer)
226 {
227 if (transfer->bits_per_word <= 8)
228 return HISI_SPI_N_BYTES_U8;
229 else if (transfer->bits_per_word <= 16)
230 return HISI_SPI_N_BYTES_U16;
231 else
232 return HISI_SPI_N_BYTES_U32;
233 }
234
hisi_spi_reader(struct hisi_spi * hs)235 static void hisi_spi_reader(struct hisi_spi *hs)
236 {
237 u32 max = min_t(u32, hs->rx_len, hs->fifo_len);
238 u32 rxw;
239
240 while (hisi_spi_rx_not_empty(hs) && max--) {
241 rxw = readl(hs->regs + HISI_SPI_DOUT);
242 /* Check the transfer's original "rx" is not null */
243 if (hs->rx) {
244 switch (hs->n_bytes) {
245 case HISI_SPI_N_BYTES_U8:
246 *(u8 *)(hs->rx) = rxw;
247 break;
248 case HISI_SPI_N_BYTES_U16:
249 *(u16 *)(hs->rx) = rxw;
250 break;
251 case HISI_SPI_N_BYTES_U32:
252 *(u32 *)(hs->rx) = rxw;
253 break;
254 }
255 hs->rx += hs->n_bytes;
256 }
257 --hs->rx_len;
258 }
259 }
260
hisi_spi_writer(struct hisi_spi * hs)261 static void hisi_spi_writer(struct hisi_spi *hs)
262 {
263 u32 max = min_t(u32, hs->tx_len, hs->fifo_len);
264 u32 txw = 0;
265
266 while (hisi_spi_tx_not_full(hs) && max--) {
267 /* Check the transfer's original "tx" is not null */
268 if (hs->tx) {
269 switch (hs->n_bytes) {
270 case HISI_SPI_N_BYTES_U8:
271 txw = *(u8 *)(hs->tx);
272 break;
273 case HISI_SPI_N_BYTES_U16:
274 txw = *(u16 *)(hs->tx);
275 break;
276 case HISI_SPI_N_BYTES_U32:
277 txw = *(u32 *)(hs->tx);
278 break;
279 }
280 hs->tx += hs->n_bytes;
281 }
282 writel(txw, hs->regs + HISI_SPI_DIN);
283 --hs->tx_len;
284 }
285 }
286
__hisi_calc_div_reg(struct hisi_chip_data * chip)287 static void __hisi_calc_div_reg(struct hisi_chip_data *chip)
288 {
289 chip->div_pre = DIV_PRE_MAX;
290 while (chip->div_pre >= DIV_PRE_MIN) {
291 if (chip->clk_div % chip->div_pre == 0)
292 break;
293
294 chip->div_pre -= 2;
295 }
296
297 if (chip->div_pre > chip->clk_div)
298 chip->div_pre = chip->clk_div;
299
300 chip->div_post = (chip->clk_div / chip->div_pre) - 1;
301 }
302
hisi_calc_effective_speed(struct spi_controller * host,struct hisi_chip_data * chip,u32 speed_hz)303 static u32 hisi_calc_effective_speed(struct spi_controller *host,
304 struct hisi_chip_data *chip, u32 speed_hz)
305 {
306 u32 effective_speed;
307
308 /* Note clock divider doesn't support odd numbers */
309 chip->clk_div = DIV_ROUND_UP(host->max_speed_hz, speed_hz) + 1;
310 chip->clk_div &= 0xfffe;
311 if (chip->clk_div > CLK_DIV_MAX)
312 chip->clk_div = CLK_DIV_MAX;
313
314 effective_speed = host->max_speed_hz / chip->clk_div;
315 if (chip->speed_hz != effective_speed) {
316 __hisi_calc_div_reg(chip);
317 chip->speed_hz = effective_speed;
318 }
319
320 return effective_speed;
321 }
322
hisi_spi_prepare_cr(struct spi_device * spi)323 static u32 hisi_spi_prepare_cr(struct spi_device *spi)
324 {
325 u32 cr = FIELD_PREP(CR_SPD_MODE_MASK, 1);
326
327 cr |= FIELD_PREP(CR_CPHA_MASK, (spi->mode & SPI_CPHA) ? 1 : 0);
328 cr |= FIELD_PREP(CR_CPOL_MASK, (spi->mode & SPI_CPOL) ? 1 : 0);
329 cr |= FIELD_PREP(CR_LOOP_MASK, (spi->mode & SPI_LOOP) ? 1 : 0);
330
331 return cr;
332 }
333
hisi_spi_hw_init(struct hisi_spi * hs)334 static void hisi_spi_hw_init(struct hisi_spi *hs)
335 {
336 hisi_spi_disable(hs);
337
338 /* FIFO default config */
339 writel(FIELD_PREP(FIFOC_TX_MASK, HISI_SPI_TX_64_OR_LESS) |
340 FIELD_PREP(FIFOC_RX_MASK, HISI_SPI_RX_16),
341 hs->regs + HISI_SPI_FIFOC);
342
343 hs->fifo_len = 256;
344 }
345
hisi_spi_irq(int irq,void * dev_id)346 static irqreturn_t hisi_spi_irq(int irq, void *dev_id)
347 {
348 struct spi_controller *host = dev_id;
349 struct hisi_spi *hs = spi_controller_get_devdata(host);
350 u32 irq_status = readl(hs->regs + HISI_SPI_ISR) & ISR_MASK;
351
352 if (!irq_status)
353 return IRQ_NONE;
354
355 if (!host->cur_msg)
356 return IRQ_HANDLED;
357
358 /* Error handling */
359 if (irq_status & ISR_RXOF) {
360 dev_err(hs->dev, "interrupt_transfer: fifo overflow\n");
361 host->cur_msg->status = -EIO;
362 goto finalize_transfer;
363 }
364
365 /*
366 * Read data from the Rx FIFO every time. If there is
367 * nothing left to receive, finalize the transfer.
368 */
369 hisi_spi_reader(hs);
370 if (!hs->rx_len)
371 goto finalize_transfer;
372
373 /* Send data out when Tx FIFO IRQ triggered */
374 if (irq_status & ISR_TX)
375 hisi_spi_writer(hs);
376
377 return IRQ_HANDLED;
378
379 finalize_transfer:
380 hisi_spi_disable(hs);
381 spi_finalize_current_transfer(host);
382 return IRQ_HANDLED;
383 }
384
hisi_spi_transfer_one(struct spi_controller * host,struct spi_device * spi,struct spi_transfer * transfer)385 static int hisi_spi_transfer_one(struct spi_controller *host,
386 struct spi_device *spi, struct spi_transfer *transfer)
387 {
388 struct hisi_spi *hs = spi_controller_get_devdata(host);
389 struct hisi_chip_data *chip = spi_get_ctldata(spi);
390 u32 cr = chip->cr;
391
392 /* Update per transfer options for speed and bpw */
393 transfer->effective_speed_hz =
394 hisi_calc_effective_speed(host, chip, transfer->speed_hz);
395 cr |= FIELD_PREP(CR_DIV_PRE_MASK, chip->div_pre);
396 cr |= FIELD_PREP(CR_DIV_POST_MASK, chip->div_post);
397 cr |= FIELD_PREP(CR_BPW_MASK, transfer->bits_per_word - 1);
398 writel(cr, hs->regs + HISI_SPI_CR);
399
400 hisi_spi_flush_fifo(hs);
401
402 hs->n_bytes = hisi_spi_n_bytes(transfer);
403 hs->tx = transfer->tx_buf;
404 hs->tx_len = transfer->len / hs->n_bytes;
405 hs->rx = transfer->rx_buf;
406 hs->rx_len = hs->tx_len;
407
408 /*
409 * Ensure that the transfer data above has been updated
410 * before the interrupt to start.
411 */
412 smp_mb();
413
414 /* Enable all interrupts and the controller */
415 writel(~(u32)IMR_MASK, hs->regs + HISI_SPI_IMR);
416 writel(1, hs->regs + HISI_SPI_ENR);
417
418 return 1;
419 }
420
hisi_spi_handle_err(struct spi_controller * host,struct spi_message * msg)421 static void hisi_spi_handle_err(struct spi_controller *host,
422 struct spi_message *msg)
423 {
424 struct hisi_spi *hs = spi_controller_get_devdata(host);
425
426 hisi_spi_disable(hs);
427
428 /*
429 * Wait for interrupt handler that is
430 * already in timeout to complete.
431 */
432 msleep(HISI_SPI_WAIT_TIMEOUT_MS);
433 }
434
hisi_spi_setup(struct spi_device * spi)435 static int hisi_spi_setup(struct spi_device *spi)
436 {
437 struct hisi_chip_data *chip;
438
439 /* Only alloc on first setup */
440 chip = spi_get_ctldata(spi);
441 if (!chip) {
442 chip = kzalloc_obj(*chip);
443 if (!chip)
444 return -ENOMEM;
445 spi_set_ctldata(spi, chip);
446 }
447
448 chip->cr = hisi_spi_prepare_cr(spi);
449
450 return 0;
451 }
452
hisi_spi_cleanup(struct spi_device * spi)453 static void hisi_spi_cleanup(struct spi_device *spi)
454 {
455 struct hisi_chip_data *chip = spi_get_ctldata(spi);
456
457 kfree(chip);
458 spi_set_ctldata(spi, NULL);
459 }
460
hisi_spi_probe(struct platform_device * pdev)461 static int hisi_spi_probe(struct platform_device *pdev)
462 {
463 struct device *dev = &pdev->dev;
464 struct spi_controller *host;
465 struct hisi_spi *hs;
466 int ret, irq;
467
468 irq = platform_get_irq(pdev, 0);
469 if (irq < 0)
470 return irq;
471
472 host = devm_spi_alloc_host(dev, sizeof(*hs));
473 if (!host)
474 return -ENOMEM;
475
476 platform_set_drvdata(pdev, host);
477
478 hs = spi_controller_get_devdata(host);
479 hs->dev = dev;
480 hs->irq = irq;
481
482 hs->regs = devm_platform_ioremap_resource(pdev, 0);
483 if (IS_ERR(hs->regs))
484 return PTR_ERR(hs->regs);
485
486 /* Specify maximum SPI clocking speed (host only) by firmware */
487 ret = device_property_read_u32(dev, "spi-max-frequency",
488 &host->max_speed_hz);
489 if (ret) {
490 dev_err(dev, "failed to get max SPI clocking speed, ret=%d\n",
491 ret);
492 return -EINVAL;
493 }
494
495 if (host->max_speed_hz == 0)
496 return dev_err_probe(dev, -EINVAL, "spi-max-frequency can't be 0\n");
497
498 ret = device_property_read_u16(dev, "num-cs",
499 &host->num_chipselect);
500 if (ret)
501 host->num_chipselect = DEFAULT_NUM_CS;
502
503 host->use_gpio_descriptors = true;
504 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
505 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
506 host->bus_num = pdev->id;
507 host->setup = hisi_spi_setup;
508 host->cleanup = hisi_spi_cleanup;
509 host->transfer_one = hisi_spi_transfer_one;
510 host->handle_err = hisi_spi_handle_err;
511 host->min_speed_hz = DIV_ROUND_UP(host->max_speed_hz, CLK_DIV_MAX);
512
513 hisi_spi_hw_init(hs);
514
515 ret = devm_request_irq(dev, hs->irq, hisi_spi_irq, 0, dev_name(dev),
516 host);
517 if (ret < 0) {
518 dev_err(dev, "failed to get IRQ=%d, ret=%d\n", hs->irq, ret);
519 return ret;
520 }
521
522 ret = spi_register_controller(host);
523 if (ret) {
524 dev_err(dev, "failed to register spi host, ret=%d\n", ret);
525 return ret;
526 }
527
528 if (hisi_spi_debugfs_init(hs))
529 dev_info(dev, "failed to create debugfs dir\n");
530
531 dev_info(dev, "hw version:0x%x max-freq:%u kHz\n",
532 readl(hs->regs + HISI_SPI_VERSION),
533 host->max_speed_hz / 1000);
534
535 return 0;
536 }
537
hisi_spi_remove(struct platform_device * pdev)538 static void hisi_spi_remove(struct platform_device *pdev)
539 {
540 struct spi_controller *host = platform_get_drvdata(pdev);
541 struct hisi_spi *hs = spi_controller_get_devdata(host);
542
543 debugfs_remove_recursive(hs->debugfs);
544 spi_unregister_controller(host);
545 }
546
547 static const struct acpi_device_id hisi_spi_acpi_match[] = {
548 {"HISI03E1", 0},
549 {}
550 };
551 MODULE_DEVICE_TABLE(acpi, hisi_spi_acpi_match);
552
553 static struct platform_driver hisi_spi_driver = {
554 .probe = hisi_spi_probe,
555 .remove = hisi_spi_remove,
556 .driver = {
557 .name = "hisi-kunpeng-spi",
558 .acpi_match_table = hisi_spi_acpi_match,
559 },
560 };
561 module_platform_driver(hisi_spi_driver);
562
563 MODULE_AUTHOR("Jay Fang <f.fangjian@huawei.com>");
564 MODULE_DESCRIPTION("HiSilicon SPI Controller Driver for Kunpeng SoCs");
565 MODULE_LICENSE("GPL v2");
566