1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // peb2466.c -- Infineon PEB2466 ALSA SoC driver
4 //
5 // Copyright 2023 CS GROUP France
6 //
7 // Author: Herve Codina <herve.codina@bootlin.com>
8
9 #include <linux/unaligned.h>
10 #include <linux/clk.h>
11 #include <linux/firmware.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/gpio/driver.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/slab.h>
17 #include <linux/spi/spi.h>
18 #include <sound/pcm_params.h>
19 #include <sound/soc.h>
20 #include <sound/tlv.h>
21
22 #define PEB2466_NB_CHANNEL 4
23
24 struct peb2466_lookup {
25 u8 (*table)[4];
26 unsigned int count;
27 };
28
29 #define PEB2466_TLV_SIZE ARRAY_SIZE(((unsigned int[]){TLV_DB_SCALE_ITEM(0, 0, 0)}))
30
31 struct peb2466_lkup_ctrl {
32 int reg;
33 unsigned int index;
34 const struct peb2466_lookup *lookup;
35 unsigned int tlv_array[PEB2466_TLV_SIZE];
36 };
37
38 struct peb2466 {
39 struct spi_device *spi;
40 struct clk *mclk;
41 struct gpio_desc *reset_gpio;
42 u8 spi_tx_buf[2 + 8]; /* Cannot use stack area for SPI (dma-safe memory) */
43 u8 spi_rx_buf[2 + 8]; /* Cannot use stack area for SPI (dma-safe memory) */
44 struct regmap *regmap;
45 struct {
46 struct peb2466_lookup ax_lookup;
47 struct peb2466_lookup ar_lookup;
48 struct peb2466_lkup_ctrl ax_lkup_ctrl;
49 struct peb2466_lkup_ctrl ar_lkup_ctrl;
50 unsigned int tg1_freq_item;
51 unsigned int tg2_freq_item;
52 } ch[PEB2466_NB_CHANNEL];
53 int max_chan_playback;
54 int max_chan_capture;
55 struct {
56 struct gpio_chip gpio_chip;
57 struct mutex lock;
58 struct {
59 unsigned int xr0;
60 unsigned int xr1;
61 unsigned int xr2;
62 unsigned int xr3;
63 } cache;
64 } gpio;
65 };
66
67 #define PEB2466_CMD_R (1 << 5)
68 #define PEB2466_CMD_W (0 << 5)
69
70 #define PEB2466_CMD_MASK 0x18
71 #define PEB2466_CMD_XOP 0x18 /* XOP is 0bxxx11xxx */
72 #define PEB2466_CMD_SOP 0x10 /* SOP is 0bxxx10xxx */
73 #define PEB2466_CMD_COP 0x00 /* COP is 0bxxx0xxxx, handle 0bxxx00xxx */
74 #define PEB2466_CMD_COP1 0x08 /* COP is 0bxxx0xxxx, handle 0bxxx01xxx */
75
76 #define PEB2466_MAKE_XOP(_lsel) (PEB2466_CMD_XOP | (_lsel))
77 #define PEB2466_MAKE_SOP(_ad, _lsel) (PEB2466_CMD_SOP | ((_ad) << 6) | (_lsel))
78 #define PEB2466_MAKE_COP(_ad, _code) (PEB2466_CMD_COP | ((_ad) << 6) | (_code))
79
80 #define PEB2466_CR0(_ch) PEB2466_MAKE_SOP(_ch, 0x0)
81 #define PEB2466_CR0_TH (1 << 7)
82 #define PEB2466_CR0_IMR1 (1 << 6)
83 #define PEB2466_CR0_FRX (1 << 5)
84 #define PEB2466_CR0_FRR (1 << 4)
85 #define PEB2466_CR0_AX (1 << 3)
86 #define PEB2466_CR0_AR (1 << 2)
87 #define PEB2466_CR0_THSEL_MASK (0x3 << 0)
88 #define PEB2466_CR0_THSEL(_set) ((_set) << 0)
89
90 #define PEB2466_CR1(_ch) PEB2466_MAKE_SOP(_ch, 0x1)
91 #define PEB2466_CR1_ETG2 (1 << 7)
92 #define PEB2466_CR1_ETG1 (1 << 6)
93 #define PEB2466_CR1_PTG2 (1 << 5)
94 #define PEB2466_CR1_PTG1 (1 << 4)
95 #define PEB2466_CR1_LAW_MASK (1 << 3)
96 #define PEB2466_CR1_LAW_ALAW (0 << 3)
97 #define PEB2466_CR1_LAW_MULAW (1 << 3)
98 #define PEB2466_CR1_PU (1 << 0)
99
100 #define PEB2466_CR2(_ch) PEB2466_MAKE_SOP(_ch, 0x2)
101 #define PEB2466_CR3(_ch) PEB2466_MAKE_SOP(_ch, 0x3)
102 #define PEB2466_CR4(_ch) PEB2466_MAKE_SOP(_ch, 0x4)
103 #define PEB2466_CR5(_ch) PEB2466_MAKE_SOP(_ch, 0x5)
104
105 #define PEB2466_XR0 PEB2466_MAKE_XOP(0x0)
106 #define PEB2466_XR1 PEB2466_MAKE_XOP(0x1)
107 #define PEB2466_XR2 PEB2466_MAKE_XOP(0x2)
108 #define PEB2466_XR3 PEB2466_MAKE_XOP(0x3)
109 #define PEB2466_XR4 PEB2466_MAKE_XOP(0x4)
110 #define PEB2466_XR5 PEB2466_MAKE_XOP(0x5)
111 #define PEB2466_XR5_MCLK_1536 (0x0 << 6)
112 #define PEB2466_XR5_MCLK_2048 (0x1 << 6)
113 #define PEB2466_XR5_MCLK_4096 (0x2 << 6)
114 #define PEB2466_XR5_MCLK_8192 (0x3 << 6)
115
116 #define PEB2466_XR6 PEB2466_MAKE_XOP(0x6)
117 #define PEB2466_XR6_PCM_OFFSET(_off) ((_off) << 0)
118
119 #define PEB2466_XR7 PEB2466_MAKE_XOP(0x7)
120
121 #define PEB2466_TH_FILTER_P1(_ch) PEB2466_MAKE_COP(_ch, 0x0)
122 #define PEB2466_TH_FILTER_P2(_ch) PEB2466_MAKE_COP(_ch, 0x1)
123 #define PEB2466_TH_FILTER_P3(_ch) PEB2466_MAKE_COP(_ch, 0x2)
124 #define PEB2466_IMR1_FILTER_P1(_ch) PEB2466_MAKE_COP(_ch, 0x4)
125 #define PEB2466_IMR1_FILTER_P2(_ch) PEB2466_MAKE_COP(_ch, 0x5)
126 #define PEB2466_FRX_FILTER(_ch) PEB2466_MAKE_COP(_ch, 0x6)
127 #define PEB2466_FRR_FILTER(_ch) PEB2466_MAKE_COP(_ch, 0x7)
128 #define PEB2466_AX_FILTER(_ch) PEB2466_MAKE_COP(_ch, 0x8)
129 #define PEB2466_AR_FILTER(_ch) PEB2466_MAKE_COP(_ch, 0x9)
130 #define PEB2466_TG1(_ch) PEB2466_MAKE_COP(_ch, 0xc)
131 #define PEB2466_TG2(_ch) PEB2466_MAKE_COP(_ch, 0xd)
132
peb2466_write_byte(struct peb2466 * peb2466,u8 cmd,u8 val)133 static int peb2466_write_byte(struct peb2466 *peb2466, u8 cmd, u8 val)
134 {
135 struct spi_transfer xfer = {
136 .tx_buf = &peb2466->spi_tx_buf,
137 .len = 2,
138 };
139
140 peb2466->spi_tx_buf[0] = cmd | PEB2466_CMD_W;
141 peb2466->spi_tx_buf[1] = val;
142
143 dev_dbg(&peb2466->spi->dev, "write byte (cmd %02x) %02x\n",
144 peb2466->spi_tx_buf[0], peb2466->spi_tx_buf[1]);
145
146 return spi_sync_transfer(peb2466->spi, &xfer, 1);
147 }
148
peb2466_read_byte(struct peb2466 * peb2466,u8 cmd,u8 * val)149 static int peb2466_read_byte(struct peb2466 *peb2466, u8 cmd, u8 *val)
150 {
151 struct spi_transfer xfer = {
152 .tx_buf = &peb2466->spi_tx_buf,
153 .rx_buf = &peb2466->spi_rx_buf,
154 .len = 3,
155 };
156 int ret;
157
158 peb2466->spi_tx_buf[0] = cmd | PEB2466_CMD_R;
159
160 ret = spi_sync_transfer(peb2466->spi, &xfer, 1);
161 if (ret)
162 return ret;
163
164 if (peb2466->spi_rx_buf[1] != 0x81) {
165 dev_err(&peb2466->spi->dev,
166 "spi xfer rd (cmd %02x) invalid ident byte (0x%02x)\n",
167 peb2466->spi_tx_buf[0], peb2466->spi_rx_buf[1]);
168 return -EILSEQ;
169 }
170
171 *val = peb2466->spi_rx_buf[2];
172
173 dev_dbg(&peb2466->spi->dev, "read byte (cmd %02x) %02x\n",
174 peb2466->spi_tx_buf[0], *val);
175
176 return 0;
177 }
178
peb2466_write_buf(struct peb2466 * peb2466,u8 cmd,const u8 * buf,unsigned int len)179 static int peb2466_write_buf(struct peb2466 *peb2466, u8 cmd, const u8 *buf, unsigned int len)
180 {
181 struct spi_transfer xfer = {
182 .tx_buf = &peb2466->spi_tx_buf,
183 .len = len + 1,
184 };
185
186 if (len > 8)
187 return -EINVAL;
188
189 peb2466->spi_tx_buf[0] = cmd | PEB2466_CMD_W;
190 memcpy(&peb2466->spi_tx_buf[1], buf, len);
191
192 dev_dbg(&peb2466->spi->dev, "write buf (cmd %02x, %u) %*ph\n",
193 peb2466->spi_tx_buf[0], len, len, &peb2466->spi_tx_buf[1]);
194
195 return spi_sync_transfer(peb2466->spi, &xfer, 1);
196 }
197
peb2466_reg_write(void * context,unsigned int reg,unsigned int val)198 static int peb2466_reg_write(void *context, unsigned int reg, unsigned int val)
199 {
200 struct peb2466 *peb2466 = context;
201 int ret;
202
203 /*
204 * Only XOP and SOP commands can be handled as registers.
205 * COP commands are handled using direct peb2466_write_buf() calls.
206 */
207 switch (reg & PEB2466_CMD_MASK) {
208 case PEB2466_CMD_XOP:
209 case PEB2466_CMD_SOP:
210 ret = peb2466_write_byte(peb2466, reg, val);
211 break;
212 default:
213 dev_err(&peb2466->spi->dev, "Not a XOP or SOP command\n");
214 ret = -EINVAL;
215 break;
216 }
217 return ret;
218 }
219
peb2466_reg_read(void * context,unsigned int reg,unsigned int * val)220 static int peb2466_reg_read(void *context, unsigned int reg, unsigned int *val)
221 {
222 struct peb2466 *peb2466 = context;
223 int ret;
224 u8 tmp;
225
226 /* Only XOP and SOP commands can be handled as registers */
227 switch (reg & PEB2466_CMD_MASK) {
228 case PEB2466_CMD_XOP:
229 case PEB2466_CMD_SOP:
230 ret = peb2466_read_byte(peb2466, reg, &tmp);
231 if (!ret)
232 *val = tmp;
233 break;
234 default:
235 dev_err(&peb2466->spi->dev, "Not a XOP or SOP command\n");
236 ret = -EINVAL;
237 break;
238 }
239 return ret;
240 }
241
242 static const struct regmap_config peb2466_regmap_config = {
243 .reg_bits = 8,
244 .val_bits = 8,
245 .max_register = 0xFF,
246 .reg_write = peb2466_reg_write,
247 .reg_read = peb2466_reg_read,
248 .cache_type = REGCACHE_NONE,
249 };
250
peb2466_lkup_ctrl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)251 static int peb2466_lkup_ctrl_info(struct snd_kcontrol *kcontrol,
252 struct snd_ctl_elem_info *uinfo)
253 {
254 struct peb2466_lkup_ctrl *lkup_ctrl =
255 (struct peb2466_lkup_ctrl *)kcontrol->private_value;
256
257 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
258 uinfo->count = 1;
259 uinfo->value.integer.min = 0;
260 uinfo->value.integer.max = lkup_ctrl->lookup->count - 1;
261 return 0;
262 }
263
peb2466_lkup_ctrl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)264 static int peb2466_lkup_ctrl_get(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_value *ucontrol)
266 {
267 struct peb2466_lkup_ctrl *lkup_ctrl =
268 (struct peb2466_lkup_ctrl *)kcontrol->private_value;
269
270 ucontrol->value.integer.value[0] = lkup_ctrl->index;
271 return 0;
272 }
273
peb2466_lkup_ctrl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)274 static int peb2466_lkup_ctrl_put(struct snd_kcontrol *kcontrol,
275 struct snd_ctl_elem_value *ucontrol)
276 {
277 struct peb2466_lkup_ctrl *lkup_ctrl =
278 (struct peb2466_lkup_ctrl *)kcontrol->private_value;
279 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
280 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
281 unsigned int index;
282 int ret;
283
284 index = ucontrol->value.integer.value[0];
285 if (index >= lkup_ctrl->lookup->count)
286 return -EINVAL;
287
288 if (index == lkup_ctrl->index)
289 return 0;
290
291 ret = peb2466_write_buf(peb2466, lkup_ctrl->reg,
292 lkup_ctrl->lookup->table[index], 4);
293 if (ret)
294 return ret;
295
296 lkup_ctrl->index = index;
297 return 1; /* The value changed */
298 }
299
peb2466_add_lkup_ctrl(struct snd_soc_component * component,struct peb2466_lkup_ctrl * lkup_ctrl,const char * name,int min_val,int step)300 static int peb2466_add_lkup_ctrl(struct snd_soc_component *component,
301 struct peb2466_lkup_ctrl *lkup_ctrl,
302 const char *name, int min_val, int step)
303 {
304 DECLARE_TLV_DB_SCALE(tlv_array, min_val, step, 0);
305 struct snd_kcontrol_new control = {0};
306
307 BUILD_BUG_ON(sizeof(lkup_ctrl->tlv_array) < sizeof(tlv_array));
308 memcpy(lkup_ctrl->tlv_array, tlv_array, sizeof(tlv_array));
309
310 control.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
311 control.name = name;
312 control.access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
313 SNDRV_CTL_ELEM_ACCESS_READWRITE;
314 control.tlv.p = lkup_ctrl->tlv_array;
315 control.info = peb2466_lkup_ctrl_info;
316 control.get = peb2466_lkup_ctrl_get;
317 control.put = peb2466_lkup_ctrl_put;
318 control.private_value = (unsigned long)lkup_ctrl;
319
320 return snd_soc_add_component_controls(component, &control, 1);
321 }
322
323 enum peb2466_tone_freq {
324 PEB2466_TONE_697HZ,
325 PEB2466_TONE_800HZ,
326 PEB2466_TONE_950HZ,
327 PEB2466_TONE_1000HZ,
328 PEB2466_TONE_1008HZ,
329 PEB2466_TONE_2000HZ,
330 };
331
332 static const u8 peb2466_tone_lookup[][4] = {
333 [PEB2466_TONE_697HZ] = {0x0a, 0x33, 0x5a, 0x2c},
334 [PEB2466_TONE_800HZ] = {0x12, 0xD6, 0x5a, 0xc0},
335 [PEB2466_TONE_950HZ] = {0x1c, 0xf0, 0x5c, 0xc0},
336 [PEB2466_TONE_1000HZ] = {0}, /* lookup value not used for 1000Hz */
337 [PEB2466_TONE_1008HZ] = {0x1a, 0xae, 0x57, 0x70},
338 [PEB2466_TONE_2000HZ] = {0x00, 0x80, 0x50, 0x09},
339 };
340
341 static const char * const peb2466_tone_freq_txt[] = {
342 [PEB2466_TONE_697HZ] = "697Hz",
343 [PEB2466_TONE_800HZ] = "800Hz",
344 [PEB2466_TONE_950HZ] = "950Hz",
345 [PEB2466_TONE_1000HZ] = "1000Hz",
346 [PEB2466_TONE_1008HZ] = "1008Hz",
347 [PEB2466_TONE_2000HZ] = "2000Hz"
348 };
349
350 static const struct soc_enum peb2466_tg_freq[][2] = {
351 [0] = {
352 SOC_ENUM_SINGLE(PEB2466_TG1(0), 0, ARRAY_SIZE(peb2466_tone_freq_txt),
353 peb2466_tone_freq_txt),
354 SOC_ENUM_SINGLE(PEB2466_TG2(0), 0, ARRAY_SIZE(peb2466_tone_freq_txt),
355 peb2466_tone_freq_txt)
356 },
357 [1] = {
358 SOC_ENUM_SINGLE(PEB2466_TG1(1), 0, ARRAY_SIZE(peb2466_tone_freq_txt),
359 peb2466_tone_freq_txt),
360 SOC_ENUM_SINGLE(PEB2466_TG2(1), 0, ARRAY_SIZE(peb2466_tone_freq_txt),
361 peb2466_tone_freq_txt)
362 },
363 [2] = {
364 SOC_ENUM_SINGLE(PEB2466_TG1(2), 0, ARRAY_SIZE(peb2466_tone_freq_txt),
365 peb2466_tone_freq_txt),
366 SOC_ENUM_SINGLE(PEB2466_TG2(2), 0, ARRAY_SIZE(peb2466_tone_freq_txt),
367 peb2466_tone_freq_txt)
368 },
369 [3] = {
370 SOC_ENUM_SINGLE(PEB2466_TG1(3), 0, ARRAY_SIZE(peb2466_tone_freq_txt),
371 peb2466_tone_freq_txt),
372 SOC_ENUM_SINGLE(PEB2466_TG2(3), 0, ARRAY_SIZE(peb2466_tone_freq_txt),
373 peb2466_tone_freq_txt)
374 }
375 };
376
peb2466_tg_freq_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)377 static int peb2466_tg_freq_get(struct snd_kcontrol *kcontrol,
378 struct snd_ctl_elem_value *ucontrol)
379 {
380 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
381 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
382 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
383
384 switch (e->reg) {
385 case PEB2466_TG1(0):
386 ucontrol->value.enumerated.item[0] = peb2466->ch[0].tg1_freq_item;
387 break;
388 case PEB2466_TG2(0):
389 ucontrol->value.enumerated.item[0] = peb2466->ch[0].tg2_freq_item;
390 break;
391 case PEB2466_TG1(1):
392 ucontrol->value.enumerated.item[0] = peb2466->ch[1].tg1_freq_item;
393 break;
394 case PEB2466_TG2(1):
395 ucontrol->value.enumerated.item[0] = peb2466->ch[1].tg2_freq_item;
396 break;
397 case PEB2466_TG1(2):
398 ucontrol->value.enumerated.item[0] = peb2466->ch[2].tg1_freq_item;
399 break;
400 case PEB2466_TG2(2):
401 ucontrol->value.enumerated.item[0] = peb2466->ch[2].tg2_freq_item;
402 break;
403 case PEB2466_TG1(3):
404 ucontrol->value.enumerated.item[0] = peb2466->ch[3].tg1_freq_item;
405 break;
406 case PEB2466_TG2(3):
407 ucontrol->value.enumerated.item[0] = peb2466->ch[3].tg2_freq_item;
408 break;
409 default:
410 return -EINVAL;
411 }
412 return 0;
413 }
414
peb2466_tg_freq_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)415 static int peb2466_tg_freq_put(struct snd_kcontrol *kcontrol,
416 struct snd_ctl_elem_value *ucontrol)
417 {
418 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
419 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
420 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
421 unsigned int *tg_freq_item;
422 u8 cr1_reg, cr1_mask;
423 unsigned int index;
424 int ret;
425
426 index = ucontrol->value.enumerated.item[0];
427
428 if (index >= ARRAY_SIZE(peb2466_tone_lookup))
429 return -EINVAL;
430
431 switch (e->reg) {
432 case PEB2466_TG1(0):
433 tg_freq_item = &peb2466->ch[0].tg1_freq_item;
434 cr1_reg = PEB2466_CR1(0);
435 cr1_mask = PEB2466_CR1_PTG1;
436 break;
437 case PEB2466_TG2(0):
438 tg_freq_item = &peb2466->ch[0].tg2_freq_item;
439 cr1_reg = PEB2466_CR1(0);
440 cr1_mask = PEB2466_CR1_PTG2;
441 break;
442 case PEB2466_TG1(1):
443 tg_freq_item = &peb2466->ch[1].tg1_freq_item;
444 cr1_reg = PEB2466_CR1(1);
445 cr1_mask = PEB2466_CR1_PTG1;
446 break;
447 case PEB2466_TG2(1):
448 tg_freq_item = &peb2466->ch[1].tg2_freq_item;
449 cr1_reg = PEB2466_CR1(1);
450 cr1_mask = PEB2466_CR1_PTG2;
451 break;
452 case PEB2466_TG1(2):
453 tg_freq_item = &peb2466->ch[2].tg1_freq_item;
454 cr1_reg = PEB2466_CR1(2);
455 cr1_mask = PEB2466_CR1_PTG1;
456 break;
457 case PEB2466_TG2(2):
458 tg_freq_item = &peb2466->ch[2].tg2_freq_item;
459 cr1_reg = PEB2466_CR1(2);
460 cr1_mask = PEB2466_CR1_PTG2;
461 break;
462 case PEB2466_TG1(3):
463 tg_freq_item = &peb2466->ch[3].tg1_freq_item;
464 cr1_reg = PEB2466_CR1(3);
465 cr1_mask = PEB2466_CR1_PTG1;
466 break;
467 case PEB2466_TG2(3):
468 tg_freq_item = &peb2466->ch[3].tg2_freq_item;
469 cr1_reg = PEB2466_CR1(3);
470 cr1_mask = PEB2466_CR1_PTG2;
471 break;
472 default:
473 return -EINVAL;
474 }
475
476 if (index == *tg_freq_item)
477 return 0;
478
479 if (index == PEB2466_TONE_1000HZ) {
480 ret = regmap_update_bits(peb2466->regmap, cr1_reg, cr1_mask, 0);
481 if (ret)
482 return ret;
483 } else {
484 ret = peb2466_write_buf(peb2466, e->reg, peb2466_tone_lookup[index], 4);
485 if (ret)
486 return ret;
487 ret = regmap_update_bits(peb2466->regmap, cr1_reg, cr1_mask, cr1_mask);
488 if (ret)
489 return ret;
490 }
491
492 *tg_freq_item = index;
493 return 1; /* The value changed */
494 }
495
496 static const struct snd_kcontrol_new peb2466_ch0_out_mix_controls[] = {
497 SOC_DAPM_SINGLE("TG1 Switch", PEB2466_CR1(0), 6, 1, 0),
498 SOC_DAPM_SINGLE("TG2 Switch", PEB2466_CR1(0), 7, 1, 0),
499 SOC_DAPM_SINGLE("Voice Switch", PEB2466_CR2(0), 0, 1, 0)
500 };
501
502 static const struct snd_kcontrol_new peb2466_ch1_out_mix_controls[] = {
503 SOC_DAPM_SINGLE("TG1 Switch", PEB2466_CR1(1), 6, 1, 0),
504 SOC_DAPM_SINGLE("TG2 Switch", PEB2466_CR1(1), 7, 1, 0),
505 SOC_DAPM_SINGLE("Voice Switch", PEB2466_CR2(1), 0, 1, 0)
506 };
507
508 static const struct snd_kcontrol_new peb2466_ch2_out_mix_controls[] = {
509 SOC_DAPM_SINGLE("TG1 Switch", PEB2466_CR1(2), 6, 1, 0),
510 SOC_DAPM_SINGLE("TG2 Switch", PEB2466_CR1(2), 7, 1, 0),
511 SOC_DAPM_SINGLE("Voice Switch", PEB2466_CR2(2), 0, 1, 0)
512 };
513
514 static const struct snd_kcontrol_new peb2466_ch3_out_mix_controls[] = {
515 SOC_DAPM_SINGLE("TG1 Switch", PEB2466_CR1(3), 6, 1, 0),
516 SOC_DAPM_SINGLE("TG2 Switch", PEB2466_CR1(3), 7, 1, 0),
517 SOC_DAPM_SINGLE("Voice Switch", PEB2466_CR2(3), 0, 1, 0)
518 };
519
520 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(peb2466_gain_p_tlv, -600, 0);
521 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(peb2466_gain_c_tlv, 0, 600);
522
523 static const struct snd_kcontrol_new peb2466_controls[] = {
524 /* Attenuators */
525 SOC_SINGLE_TLV("DAC0 -6dB Playback Volume", PEB2466_CR3(0), 2, 1, 1, peb2466_gain_p_tlv),
526 SOC_SINGLE_TLV("DAC1 -6dB Playback Volume", PEB2466_CR3(1), 2, 1, 1, peb2466_gain_p_tlv),
527 SOC_SINGLE_TLV("DAC2 -6dB Playback Volume", PEB2466_CR3(2), 2, 1, 1, peb2466_gain_p_tlv),
528 SOC_SINGLE_TLV("DAC3 -6dB Playback Volume", PEB2466_CR3(3), 2, 1, 1, peb2466_gain_p_tlv),
529
530 /* Amplifiers */
531 SOC_SINGLE_TLV("ADC0 +6dB Capture Volume", PEB2466_CR3(0), 3, 1, 0, peb2466_gain_c_tlv),
532 SOC_SINGLE_TLV("ADC1 +6dB Capture Volume", PEB2466_CR3(1), 3, 1, 0, peb2466_gain_c_tlv),
533 SOC_SINGLE_TLV("ADC2 +6dB Capture Volume", PEB2466_CR3(2), 3, 1, 0, peb2466_gain_c_tlv),
534 SOC_SINGLE_TLV("ADC3 +6dB Capture Volume", PEB2466_CR3(3), 3, 1, 0, peb2466_gain_c_tlv),
535
536 /* Tone generators */
537 SOC_ENUM_EXT("DAC0 TG1 Freq", peb2466_tg_freq[0][0],
538 peb2466_tg_freq_get, peb2466_tg_freq_put),
539 SOC_ENUM_EXT("DAC1 TG1 Freq", peb2466_tg_freq[1][0],
540 peb2466_tg_freq_get, peb2466_tg_freq_put),
541 SOC_ENUM_EXT("DAC2 TG1 Freq", peb2466_tg_freq[2][0],
542 peb2466_tg_freq_get, peb2466_tg_freq_put),
543 SOC_ENUM_EXT("DAC3 TG1 Freq", peb2466_tg_freq[3][0],
544 peb2466_tg_freq_get, peb2466_tg_freq_put),
545
546 SOC_ENUM_EXT("DAC0 TG2 Freq", peb2466_tg_freq[0][1],
547 peb2466_tg_freq_get, peb2466_tg_freq_put),
548 SOC_ENUM_EXT("DAC1 TG2 Freq", peb2466_tg_freq[1][1],
549 peb2466_tg_freq_get, peb2466_tg_freq_put),
550 SOC_ENUM_EXT("DAC2 TG2 Freq", peb2466_tg_freq[2][1],
551 peb2466_tg_freq_get, peb2466_tg_freq_put),
552 SOC_ENUM_EXT("DAC3 TG2 Freq", peb2466_tg_freq[3][1],
553 peb2466_tg_freq_get, peb2466_tg_freq_put),
554 };
555
556 static const struct snd_soc_dapm_widget peb2466_dapm_widgets[] = {
557 SND_SOC_DAPM_SUPPLY("CH0 PWR", PEB2466_CR1(0), 0, 0, NULL, 0),
558 SND_SOC_DAPM_SUPPLY("CH1 PWR", PEB2466_CR1(1), 0, 0, NULL, 0),
559 SND_SOC_DAPM_SUPPLY("CH2 PWR", PEB2466_CR1(2), 0, 0, NULL, 0),
560 SND_SOC_DAPM_SUPPLY("CH3 PWR", PEB2466_CR1(3), 0, 0, NULL, 0),
561
562 SND_SOC_DAPM_DAC("CH0 DIN", "Playback", SND_SOC_NOPM, 0, 0),
563 SND_SOC_DAPM_DAC("CH1 DIN", "Playback", SND_SOC_NOPM, 0, 0),
564 SND_SOC_DAPM_DAC("CH2 DIN", "Playback", SND_SOC_NOPM, 0, 0),
565 SND_SOC_DAPM_DAC("CH3 DIN", "Playback", SND_SOC_NOPM, 0, 0),
566
567 SND_SOC_DAPM_SIGGEN("CH0 TG1"),
568 SND_SOC_DAPM_SIGGEN("CH1 TG1"),
569 SND_SOC_DAPM_SIGGEN("CH2 TG1"),
570 SND_SOC_DAPM_SIGGEN("CH3 TG1"),
571
572 SND_SOC_DAPM_SIGGEN("CH0 TG2"),
573 SND_SOC_DAPM_SIGGEN("CH1 TG2"),
574 SND_SOC_DAPM_SIGGEN("CH2 TG2"),
575 SND_SOC_DAPM_SIGGEN("CH3 TG2"),
576
577 SND_SOC_DAPM_MIXER("DAC0 Mixer", SND_SOC_NOPM, 0, 0,
578 peb2466_ch0_out_mix_controls,
579 ARRAY_SIZE(peb2466_ch0_out_mix_controls)),
580 SND_SOC_DAPM_MIXER("DAC1 Mixer", SND_SOC_NOPM, 0, 0,
581 peb2466_ch1_out_mix_controls,
582 ARRAY_SIZE(peb2466_ch1_out_mix_controls)),
583 SND_SOC_DAPM_MIXER("DAC2 Mixer", SND_SOC_NOPM, 0, 0,
584 peb2466_ch2_out_mix_controls,
585 ARRAY_SIZE(peb2466_ch2_out_mix_controls)),
586 SND_SOC_DAPM_MIXER("DAC3 Mixer", SND_SOC_NOPM, 0, 0,
587 peb2466_ch3_out_mix_controls,
588 ARRAY_SIZE(peb2466_ch3_out_mix_controls)),
589
590 SND_SOC_DAPM_PGA("DAC0 PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
591 SND_SOC_DAPM_PGA("DAC1 PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
592 SND_SOC_DAPM_PGA("DAC2 PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
593 SND_SOC_DAPM_PGA("DAC3 PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
594
595 SND_SOC_DAPM_OUTPUT("OUT0"),
596 SND_SOC_DAPM_OUTPUT("OUT1"),
597 SND_SOC_DAPM_OUTPUT("OUT2"),
598 SND_SOC_DAPM_OUTPUT("OUT3"),
599
600 SND_SOC_DAPM_INPUT("IN0"),
601 SND_SOC_DAPM_INPUT("IN1"),
602 SND_SOC_DAPM_INPUT("IN2"),
603 SND_SOC_DAPM_INPUT("IN3"),
604
605 SND_SOC_DAPM_DAC("ADC0", "Capture", SND_SOC_NOPM, 0, 0),
606 SND_SOC_DAPM_DAC("ADC1", "Capture", SND_SOC_NOPM, 0, 0),
607 SND_SOC_DAPM_DAC("ADC2", "Capture", SND_SOC_NOPM, 0, 0),
608 SND_SOC_DAPM_DAC("ADC3", "Capture", SND_SOC_NOPM, 0, 0),
609 };
610
611 static const struct snd_soc_dapm_route peb2466_dapm_routes[] = {
612 { "CH0 DIN", NULL, "CH0 PWR" },
613 { "CH1 DIN", NULL, "CH1 PWR" },
614 { "CH2 DIN", NULL, "CH2 PWR" },
615 { "CH3 DIN", NULL, "CH3 PWR" },
616
617 { "CH0 TG1", NULL, "CH0 PWR" },
618 { "CH1 TG1", NULL, "CH1 PWR" },
619 { "CH2 TG1", NULL, "CH2 PWR" },
620 { "CH3 TG1", NULL, "CH3 PWR" },
621
622 { "CH0 TG2", NULL, "CH0 PWR" },
623 { "CH1 TG2", NULL, "CH1 PWR" },
624 { "CH2 TG2", NULL, "CH2 PWR" },
625 { "CH3 TG2", NULL, "CH3 PWR" },
626
627 { "DAC0 Mixer", "TG1 Switch", "CH0 TG1" },
628 { "DAC0 Mixer", "TG2 Switch", "CH0 TG2" },
629 { "DAC0 Mixer", "Voice Switch", "CH0 DIN" },
630 { "DAC0 Mixer", NULL, "CH0 DIN" },
631
632 { "DAC1 Mixer", "TG1 Switch", "CH1 TG1" },
633 { "DAC1 Mixer", "TG2 Switch", "CH1 TG2" },
634 { "DAC1 Mixer", "Voice Switch", "CH1 DIN" },
635 { "DAC1 Mixer", NULL, "CH1 DIN" },
636
637 { "DAC2 Mixer", "TG1 Switch", "CH2 TG1" },
638 { "DAC2 Mixer", "TG2 Switch", "CH2 TG2" },
639 { "DAC2 Mixer", "Voice Switch", "CH2 DIN" },
640 { "DAC2 Mixer", NULL, "CH2 DIN" },
641
642 { "DAC3 Mixer", "TG1 Switch", "CH3 TG1" },
643 { "DAC3 Mixer", "TG2 Switch", "CH3 TG2" },
644 { "DAC3 Mixer", "Voice Switch", "CH3 DIN" },
645 { "DAC3 Mixer", NULL, "CH3 DIN" },
646
647 { "DAC0 PGA", NULL, "DAC0 Mixer" },
648 { "DAC1 PGA", NULL, "DAC1 Mixer" },
649 { "DAC2 PGA", NULL, "DAC2 Mixer" },
650 { "DAC3 PGA", NULL, "DAC3 Mixer" },
651
652 { "OUT0", NULL, "DAC0 PGA" },
653 { "OUT1", NULL, "DAC1 PGA" },
654 { "OUT2", NULL, "DAC2 PGA" },
655 { "OUT3", NULL, "DAC3 PGA" },
656
657 { "ADC0", NULL, "IN0" },
658 { "ADC1", NULL, "IN1" },
659 { "ADC2", NULL, "IN2" },
660 { "ADC3", NULL, "IN3" },
661
662 { "ADC0", NULL, "CH0 PWR" },
663 { "ADC1", NULL, "CH1 PWR" },
664 { "ADC2", NULL, "CH2 PWR" },
665 { "ADC3", NULL, "CH3 PWR" },
666 };
667
peb2466_dai_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int width)668 static int peb2466_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
669 unsigned int rx_mask, int slots, int width)
670 {
671 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(dai->component);
672 unsigned int chan;
673 unsigned int mask;
674 u8 slot;
675 int ret;
676
677 switch (width) {
678 case 0:
679 /* Not set -> default 8 */
680 case 8:
681 break;
682 default:
683 dev_err(dai->dev, "tdm slot width %d not supported\n", width);
684 return -EINVAL;
685 }
686
687 mask = tx_mask;
688 slot = 0;
689 chan = 0;
690 while (mask && chan < PEB2466_NB_CHANNEL) {
691 if (mask & 0x1) {
692 ret = regmap_write(peb2466->regmap, PEB2466_CR5(chan), slot);
693 if (ret) {
694 dev_err(dai->dev, "chan %d set tx tdm slot failed (%d)\n",
695 chan, ret);
696 return ret;
697 }
698 chan++;
699 }
700 mask >>= 1;
701 slot++;
702 }
703 if (mask) {
704 dev_err(dai->dev, "too much tx slots defined (mask = 0x%x) support max %d\n",
705 tx_mask, PEB2466_NB_CHANNEL);
706 return -EINVAL;
707 }
708 peb2466->max_chan_playback = chan;
709
710 mask = rx_mask;
711 slot = 0;
712 chan = 0;
713 while (mask && chan < PEB2466_NB_CHANNEL) {
714 if (mask & 0x1) {
715 ret = regmap_write(peb2466->regmap, PEB2466_CR4(chan), slot);
716 if (ret) {
717 dev_err(dai->dev, "chan %d set rx tdm slot failed (%d)\n",
718 chan, ret);
719 return ret;
720 }
721 chan++;
722 }
723 mask >>= 1;
724 slot++;
725 }
726 if (mask) {
727 dev_err(dai->dev, "too much rx slots defined (mask = 0x%x) support max %d\n",
728 rx_mask, PEB2466_NB_CHANNEL);
729 return -EINVAL;
730 }
731 peb2466->max_chan_capture = chan;
732
733 return 0;
734 }
735
peb2466_dai_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)736 static int peb2466_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
737 {
738 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(dai->component);
739 u8 xr6;
740
741 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
742 case SND_SOC_DAIFMT_DSP_A:
743 xr6 = PEB2466_XR6_PCM_OFFSET(1);
744 break;
745 case SND_SOC_DAIFMT_DSP_B:
746 xr6 = PEB2466_XR6_PCM_OFFSET(0);
747 break;
748 default:
749 dev_err(dai->dev, "Unsupported format 0x%x\n",
750 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
751 return -EINVAL;
752 }
753 return regmap_write(peb2466->regmap, PEB2466_XR6, xr6);
754 }
755
peb2466_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)756 static int peb2466_dai_hw_params(struct snd_pcm_substream *substream,
757 struct snd_pcm_hw_params *params,
758 struct snd_soc_dai *dai)
759 {
760 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(dai->component);
761 unsigned int ch;
762 int ret;
763 u8 cr1;
764
765 switch (params_format(params)) {
766 case SNDRV_PCM_FORMAT_MU_LAW:
767 cr1 = PEB2466_CR1_LAW_MULAW;
768 break;
769 case SNDRV_PCM_FORMAT_A_LAW:
770 cr1 = PEB2466_CR1_LAW_ALAW;
771 break;
772 default:
773 dev_err(&peb2466->spi->dev, "Unsupported format 0x%x\n",
774 params_format(params));
775 return -EINVAL;
776 }
777
778 for (ch = 0; ch < PEB2466_NB_CHANNEL; ch++) {
779 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR1(ch),
780 PEB2466_CR1_LAW_MASK, cr1);
781 if (ret)
782 return ret;
783 }
784
785 return 0;
786 }
787
788 static const unsigned int peb2466_sample_bits[] = {8};
789
790 static struct snd_pcm_hw_constraint_list peb2466_sample_bits_constr = {
791 .list = peb2466_sample_bits,
792 .count = ARRAY_SIZE(peb2466_sample_bits),
793 };
794
peb2466_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)795 static int peb2466_dai_startup(struct snd_pcm_substream *substream,
796 struct snd_soc_dai *dai)
797 {
798 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(dai->component);
799 unsigned int max_ch;
800 int ret;
801
802 max_ch = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
803 peb2466->max_chan_playback : peb2466->max_chan_capture;
804
805 /*
806 * Disable stream support (min = 0, max = 0) if no timeslots were
807 * configured.
808 */
809 ret = snd_pcm_hw_constraint_minmax(substream->runtime,
810 SNDRV_PCM_HW_PARAM_CHANNELS,
811 max_ch ? 1 : 0, max_ch);
812 if (ret < 0)
813 return ret;
814
815 return snd_pcm_hw_constraint_list(substream->runtime, 0,
816 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
817 &peb2466_sample_bits_constr);
818 }
819
820 static const u64 peb2466_dai_formats[] = {
821 SND_SOC_POSSIBLE_DAIFMT_DSP_A |
822 SND_SOC_POSSIBLE_DAIFMT_DSP_B,
823 };
824
825 static const struct snd_soc_dai_ops peb2466_dai_ops = {
826 .startup = peb2466_dai_startup,
827 .hw_params = peb2466_dai_hw_params,
828 .set_tdm_slot = peb2466_dai_set_tdm_slot,
829 .set_fmt = peb2466_dai_set_fmt,
830 .auto_selectable_formats = peb2466_dai_formats,
831 .num_auto_selectable_formats = ARRAY_SIZE(peb2466_dai_formats),
832 };
833
834 static struct snd_soc_dai_driver peb2466_dai_driver = {
835 .name = "peb2466",
836 .playback = {
837 .stream_name = "Playback",
838 .channels_min = 1,
839 .channels_max = PEB2466_NB_CHANNEL,
840 .rates = SNDRV_PCM_RATE_8000,
841 .formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW,
842 },
843 .capture = {
844 .stream_name = "Capture",
845 .channels_min = 1,
846 .channels_max = PEB2466_NB_CHANNEL,
847 .rates = SNDRV_PCM_RATE_8000,
848 .formats = SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW,
849 },
850 .ops = &peb2466_dai_ops,
851 };
852
peb2466_reset_audio(struct peb2466 * peb2466)853 static int peb2466_reset_audio(struct peb2466 *peb2466)
854 {
855 static const struct reg_sequence reg_reset[] = {
856 { .reg = PEB2466_XR6, .def = 0x00 },
857
858 { .reg = PEB2466_CR5(0), .def = 0x00 },
859 { .reg = PEB2466_CR4(0), .def = 0x00 },
860 { .reg = PEB2466_CR3(0), .def = 0x00 },
861 { .reg = PEB2466_CR2(0), .def = 0x00 },
862 { .reg = PEB2466_CR1(0), .def = 0x00 },
863 { .reg = PEB2466_CR0(0), .def = PEB2466_CR0_IMR1 },
864
865 { .reg = PEB2466_CR5(1), .def = 0x00 },
866 { .reg = PEB2466_CR4(1), .def = 0x00 },
867 { .reg = PEB2466_CR3(1), .def = 0x00 },
868 { .reg = PEB2466_CR2(1), .def = 0x00 },
869 { .reg = PEB2466_CR1(1), .def = 0x00 },
870 { .reg = PEB2466_CR0(1), .def = PEB2466_CR0_IMR1 },
871
872 { .reg = PEB2466_CR5(2), .def = 0x00 },
873 { .reg = PEB2466_CR4(2), .def = 0x00 },
874 { .reg = PEB2466_CR3(2), .def = 0x00 },
875 { .reg = PEB2466_CR2(2), .def = 0x00 },
876 { .reg = PEB2466_CR1(2), .def = 0x00 },
877 { .reg = PEB2466_CR0(2), .def = PEB2466_CR0_IMR1 },
878
879 { .reg = PEB2466_CR5(3), .def = 0x00 },
880 { .reg = PEB2466_CR4(3), .def = 0x00 },
881 { .reg = PEB2466_CR3(3), .def = 0x00 },
882 { .reg = PEB2466_CR2(3), .def = 0x00 },
883 { .reg = PEB2466_CR1(3), .def = 0x00 },
884 { .reg = PEB2466_CR0(3), .def = PEB2466_CR0_IMR1 },
885 };
886 static const u8 imr1_p1[8] = {0x00, 0x90, 0x09, 0x00, 0x90, 0x09, 0x00, 0x00};
887 static const u8 imr1_p2[8] = {0x7F, 0xFF, 0x00, 0x00, 0x90, 0x14, 0x40, 0x08};
888 static const u8 zero[8] = {0};
889 int ret;
890 int i;
891
892 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
893 peb2466->ch[i].tg1_freq_item = PEB2466_TONE_1000HZ;
894 peb2466->ch[i].tg2_freq_item = PEB2466_TONE_1000HZ;
895
896 /*
897 * Even if not used, disabling IM/R1 filter is not recommended.
898 * Instead, we must configure it with default coefficients and
899 * enable it.
900 * The filter will be enabled right after (in the following
901 * regmap_multi_reg_write() call).
902 */
903 ret = peb2466_write_buf(peb2466, PEB2466_IMR1_FILTER_P1(i), imr1_p1, 8);
904 if (ret)
905 return ret;
906 ret = peb2466_write_buf(peb2466, PEB2466_IMR1_FILTER_P2(i), imr1_p2, 8);
907 if (ret)
908 return ret;
909
910 /* Set all other filters coefficients to zero */
911 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P1(i), zero, 8);
912 if (ret)
913 return ret;
914 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P2(i), zero, 8);
915 if (ret)
916 return ret;
917 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P3(i), zero, 8);
918 if (ret)
919 return ret;
920 ret = peb2466_write_buf(peb2466, PEB2466_FRX_FILTER(i), zero, 8);
921 if (ret)
922 return ret;
923 ret = peb2466_write_buf(peb2466, PEB2466_FRR_FILTER(i), zero, 8);
924 if (ret)
925 return ret;
926 ret = peb2466_write_buf(peb2466, PEB2466_AX_FILTER(i), zero, 4);
927 if (ret)
928 return ret;
929 ret = peb2466_write_buf(peb2466, PEB2466_AR_FILTER(i), zero, 4);
930 if (ret)
931 return ret;
932 }
933
934 return regmap_multi_reg_write(peb2466->regmap, reg_reset, ARRAY_SIZE(reg_reset));
935 }
936
peb2466_fw_parse_thfilter(struct snd_soc_component * component,u16 tag,u32 lng,const u8 * data)937 static int peb2466_fw_parse_thfilter(struct snd_soc_component *component,
938 u16 tag, u32 lng, const u8 *data)
939 {
940 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
941 u8 mask;
942 int ret;
943 int i;
944
945 dev_info(component->dev, "fw TH filter: mask %x, %*phN\n", *data,
946 lng - 1, data + 1);
947
948 /*
949 * TH_FILTER TLV data:
950 * - @0 1 byte: Chan mask (bit set means related channel is concerned)
951 * - @1 8 bytes: TH-Filter coefficients part1
952 * - @9 8 bytes: TH-Filter coefficients part2
953 * - @17 8 bytes: TH-Filter coefficients part3
954 */
955 mask = *data;
956 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
957 if (!(mask & (1 << i)))
958 continue;
959
960 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
961 PEB2466_CR0_TH, 0);
962 if (ret)
963 return ret;
964
965 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P1(i), data + 1, 8);
966 if (ret)
967 return ret;
968
969 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P2(i), data + 9, 8);
970 if (ret)
971 return ret;
972
973 ret = peb2466_write_buf(peb2466, PEB2466_TH_FILTER_P3(i), data + 17, 8);
974 if (ret)
975 return ret;
976
977 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
978 PEB2466_CR0_TH | PEB2466_CR0_THSEL_MASK,
979 PEB2466_CR0_TH | PEB2466_CR0_THSEL(i));
980 if (ret)
981 return ret;
982 }
983 return 0;
984 }
985
peb2466_fw_parse_imr1filter(struct snd_soc_component * component,u16 tag,u32 lng,const u8 * data)986 static int peb2466_fw_parse_imr1filter(struct snd_soc_component *component,
987 u16 tag, u32 lng, const u8 *data)
988 {
989 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
990 u8 mask;
991 int ret;
992 int i;
993
994 dev_info(component->dev, "fw IM/R1 filter: mask %x, %*phN\n", *data,
995 lng - 1, data + 1);
996
997 /*
998 * IMR1_FILTER TLV data:
999 * - @0 1 byte: Chan mask (bit set means related channel is concerned)
1000 * - @1 8 bytes: IM/R1-Filter coefficients part1
1001 * - @9 8 bytes: IM/R1-Filter coefficients part2
1002 */
1003 mask = *data;
1004 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
1005 if (!(mask & (1 << i)))
1006 continue;
1007
1008 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
1009 PEB2466_CR0_IMR1, 0);
1010 if (ret)
1011 return ret;
1012
1013 ret = peb2466_write_buf(peb2466, PEB2466_IMR1_FILTER_P1(i), data + 1, 8);
1014 if (ret)
1015 return ret;
1016
1017 ret = peb2466_write_buf(peb2466, PEB2466_IMR1_FILTER_P2(i), data + 9, 8);
1018 if (ret)
1019 return ret;
1020
1021 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
1022 PEB2466_CR0_IMR1, PEB2466_CR0_IMR1);
1023 if (ret)
1024 return ret;
1025 }
1026 return 0;
1027 }
1028
peb2466_fw_parse_frxfilter(struct snd_soc_component * component,u16 tag,u32 lng,const u8 * data)1029 static int peb2466_fw_parse_frxfilter(struct snd_soc_component *component,
1030 u16 tag, u32 lng, const u8 *data)
1031 {
1032 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
1033 u8 mask;
1034 int ret;
1035 int i;
1036
1037 dev_info(component->dev, "fw FRX filter: mask %x, %*phN\n", *data,
1038 lng - 1, data + 1);
1039
1040 /*
1041 * FRX_FILTER TLV data:
1042 * - @0 1 byte: Chan mask (bit set means related channel is concerned)
1043 * - @1 8 bytes: FRX-Filter coefficients
1044 */
1045 mask = *data;
1046 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
1047 if (!(mask & (1 << i)))
1048 continue;
1049
1050 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
1051 PEB2466_CR0_FRX, 0);
1052 if (ret)
1053 return ret;
1054
1055 ret = peb2466_write_buf(peb2466, PEB2466_FRX_FILTER(i), data + 1, 8);
1056 if (ret)
1057 return ret;
1058
1059 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
1060 PEB2466_CR0_FRX, PEB2466_CR0_FRX);
1061 if (ret)
1062 return ret;
1063 }
1064 return 0;
1065 }
1066
peb2466_fw_parse_frrfilter(struct snd_soc_component * component,u16 tag,u32 lng,const u8 * data)1067 static int peb2466_fw_parse_frrfilter(struct snd_soc_component *component,
1068 u16 tag, u32 lng, const u8 *data)
1069 {
1070 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
1071 u8 mask;
1072 int ret;
1073 int i;
1074
1075 dev_info(component->dev, "fw FRR filter: mask %x, %*phN\n", *data,
1076 lng - 1, data + 1);
1077
1078 /*
1079 * FRR_FILTER TLV data:
1080 * - @0 1 byte: Chan mask (bit set means related channel is concerned)
1081 * - @1 8 bytes: FRR-Filter coefficients
1082 */
1083 mask = *data;
1084 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
1085 if (!(mask & (1 << i)))
1086 continue;
1087
1088 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
1089 PEB2466_CR0_FRR, 0);
1090 if (ret)
1091 return ret;
1092
1093 ret = peb2466_write_buf(peb2466, PEB2466_FRR_FILTER(i), data + 1, 8);
1094 if (ret)
1095 return ret;
1096
1097 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
1098 PEB2466_CR0_FRR, PEB2466_CR0_FRR);
1099 if (ret)
1100 return ret;
1101 }
1102 return 0;
1103 }
1104
peb2466_fw_parse_axfilter(struct snd_soc_component * component,u16 tag,u32 lng,const u8 * data)1105 static int peb2466_fw_parse_axfilter(struct snd_soc_component *component,
1106 u16 tag, u32 lng, const u8 *data)
1107 {
1108 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
1109 u8 mask;
1110 int ret;
1111 int i;
1112
1113 dev_info(component->dev, "fw AX filter: mask %x, %*phN\n", *data,
1114 lng - 1, data + 1);
1115
1116 /*
1117 * AX_FILTER TLV data:
1118 * - @0 1 byte: Chan mask (bit set means related channel is concerned)
1119 * - @1 4 bytes: AX-Filter coefficients
1120 */
1121 mask = *data;
1122 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
1123 if (!(mask & (1 << i)))
1124 continue;
1125
1126 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
1127 PEB2466_CR0_AX, 0);
1128 if (ret)
1129 return ret;
1130
1131 ret = peb2466_write_buf(peb2466, PEB2466_AX_FILTER(i), data + 1, 4);
1132 if (ret)
1133 return ret;
1134
1135 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
1136 PEB2466_CR0_AX, PEB2466_CR0_AX);
1137 if (ret)
1138 return ret;
1139 }
1140 return 0;
1141 }
1142
peb2466_fw_parse_arfilter(struct snd_soc_component * component,u16 tag,u32 lng,const u8 * data)1143 static int peb2466_fw_parse_arfilter(struct snd_soc_component *component,
1144 u16 tag, u32 lng, const u8 *data)
1145 {
1146 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
1147 u8 mask;
1148 int ret;
1149 int i;
1150
1151 dev_info(component->dev, "fw AR filter: mask %x, %*phN\n", *data,
1152 lng - 1, data + 1);
1153
1154 /*
1155 * AR_FILTER TLV data:
1156 * - @0 1 byte: Chan mask (bit set means related channel is concerned)
1157 * - @1 4 bytes: AR-Filter coefficients
1158 */
1159 mask = *data;
1160 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
1161 if (!(mask & (1 << i)))
1162 continue;
1163
1164 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
1165 PEB2466_CR0_AR, 0);
1166 if (ret)
1167 return ret;
1168
1169 ret = peb2466_write_buf(peb2466, PEB2466_AR_FILTER(i), data + 1, 4);
1170 if (ret)
1171 return ret;
1172
1173 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
1174 PEB2466_CR0_AR, PEB2466_CR0_AR);
1175 if (ret)
1176 return ret;
1177 }
1178 return 0;
1179 }
1180
1181 static const char * const peb2466_ax_ctrl_names[] = {
1182 "ADC0 Capture Volume",
1183 "ADC1 Capture Volume",
1184 "ADC2 Capture Volume",
1185 "ADC3 Capture Volume",
1186 };
1187
peb2466_fw_parse_axtable(struct snd_soc_component * component,u16 tag,u32 lng,const u8 * data)1188 static int peb2466_fw_parse_axtable(struct snd_soc_component *component,
1189 u16 tag, u32 lng, const u8 *data)
1190 {
1191 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
1192 struct peb2466_lkup_ctrl *lkup_ctrl;
1193 struct peb2466_lookup *lookup;
1194 u8 (*table)[4];
1195 u32 table_size;
1196 u32 init_index;
1197 s32 min_val;
1198 s32 step;
1199 u8 mask;
1200 int ret;
1201 int i;
1202
1203 /*
1204 * AX_TABLE TLV data:
1205 * - @0 1 byte: Chan mask (bit set means related channel is concerned)
1206 * - @1 32bits signed: Min table value in centi dB (MinVal)
1207 * ie -300 means -3.0 dB
1208 * - @5 32bits signed: Step from on item to other item in centi dB (Step)
1209 * ie 25 means 0.25 dB)
1210 * - @9 32bits unsigned: Item index in the table to use for the initial
1211 * value
1212 * - @13 N*4 bytes: Table composed of 4 bytes items.
1213 * Each item correspond to an AX filter value.
1214 *
1215 * The conversion from raw value item in the table to/from the value in
1216 * dB is: Raw value at index i <-> (MinVal + i * Step) in centi dB.
1217 */
1218
1219 /* Check Lng and extract the table size. */
1220 if (lng < 13 || ((lng - 13) % 4)) {
1221 dev_err(component->dev, "fw AX table lng %u invalid\n", lng);
1222 return -EINVAL;
1223 }
1224 table_size = lng - 13;
1225
1226 min_val = get_unaligned_be32(data + 1);
1227 step = get_unaligned_be32(data + 5);
1228 init_index = get_unaligned_be32(data + 9);
1229 if (init_index >= (table_size / 4)) {
1230 dev_err(component->dev, "fw AX table index %u out of table[%u]\n",
1231 init_index, table_size / 4);
1232 return -EINVAL;
1233 }
1234
1235 dev_info(component->dev,
1236 "fw AX table: mask %x, min %d, step %d, %u items, tbl[%u] %*phN\n",
1237 *data, min_val, step, table_size / 4, init_index,
1238 4, data + 13 + (init_index * 4));
1239
1240 BUILD_BUG_ON(sizeof(*table) != 4);
1241 table = devm_kzalloc(&peb2466->spi->dev, table_size, GFP_KERNEL);
1242 if (!table)
1243 return -ENOMEM;
1244 memcpy(table, data + 13, table_size);
1245
1246 mask = *data;
1247 BUILD_BUG_ON(ARRAY_SIZE(peb2466_ax_ctrl_names) != ARRAY_SIZE(peb2466->ch));
1248 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
1249 if (!(mask & (1 << i)))
1250 continue;
1251
1252 lookup = &peb2466->ch[i].ax_lookup;
1253 lookup->table = table;
1254 lookup->count = table_size / 4;
1255
1256 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
1257 PEB2466_CR0_AX, 0);
1258 if (ret)
1259 return ret;
1260
1261 ret = peb2466_write_buf(peb2466, PEB2466_AX_FILTER(i),
1262 lookup->table[init_index], 4);
1263 if (ret)
1264 return ret;
1265
1266 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
1267 PEB2466_CR0_AX, PEB2466_CR0_AX);
1268 if (ret)
1269 return ret;
1270
1271 lkup_ctrl = &peb2466->ch[i].ax_lkup_ctrl;
1272 lkup_ctrl->lookup = lookup;
1273 lkup_ctrl->reg = PEB2466_AX_FILTER(i);
1274 lkup_ctrl->index = init_index;
1275
1276 ret = peb2466_add_lkup_ctrl(component, lkup_ctrl,
1277 peb2466_ax_ctrl_names[i],
1278 min_val, step);
1279 if (ret)
1280 return ret;
1281 }
1282 return 0;
1283 }
1284
1285 static const char * const peb2466_ar_ctrl_names[] = {
1286 "DAC0 Playback Volume",
1287 "DAC1 Playback Volume",
1288 "DAC2 Playback Volume",
1289 "DAC3 Playback Volume",
1290 };
1291
peb2466_fw_parse_artable(struct snd_soc_component * component,u16 tag,u32 lng,const u8 * data)1292 static int peb2466_fw_parse_artable(struct snd_soc_component *component,
1293 u16 tag, u32 lng, const u8 *data)
1294 {
1295 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
1296 struct peb2466_lkup_ctrl *lkup_ctrl;
1297 struct peb2466_lookup *lookup;
1298 u8 (*table)[4];
1299 u32 table_size;
1300 u32 init_index;
1301 s32 min_val;
1302 s32 step;
1303 u8 mask;
1304 int ret;
1305 int i;
1306
1307 /*
1308 * AR_TABLE TLV data:
1309 * - @0 1 byte: Chan mask (bit set means related channel is concerned)
1310 * - @1 32bits signed: Min table value in centi dB (MinVal)
1311 * ie -300 means -3.0 dB
1312 * - @5 32bits signed: Step from on item to other item in centi dB (Step)
1313 * ie 25 means 0.25 dB)
1314 * - @9 32bits unsigned: Item index in the table to use for the initial
1315 * value
1316 * - @13 N*4 bytes: Table composed of 4 bytes items.
1317 * Each item correspond to an AR filter value.
1318 *
1319 * The conversion from raw value item in the table to/from the value in
1320 * dB is: Raw value at index i <-> (MinVal + i * Step) in centi dB.
1321 */
1322
1323 /* Check Lng and extract the table size. */
1324 if (lng < 13 || ((lng - 13) % 4)) {
1325 dev_err(component->dev, "fw AR table lng %u invalid\n", lng);
1326 return -EINVAL;
1327 }
1328 table_size = lng - 13;
1329
1330 min_val = get_unaligned_be32(data + 1);
1331 step = get_unaligned_be32(data + 5);
1332 init_index = get_unaligned_be32(data + 9);
1333 if (init_index >= (table_size / 4)) {
1334 dev_err(component->dev, "fw AR table index %u out of table[%u]\n",
1335 init_index, table_size / 4);
1336 return -EINVAL;
1337 }
1338
1339 dev_info(component->dev,
1340 "fw AR table: mask %x, min %d, step %d, %u items, tbl[%u] %*phN\n",
1341 *data, min_val, step, table_size / 4, init_index,
1342 4, data + 13 + (init_index * 4));
1343
1344 BUILD_BUG_ON(sizeof(*table) != 4);
1345 table = devm_kzalloc(&peb2466->spi->dev, table_size, GFP_KERNEL);
1346 if (!table)
1347 return -ENOMEM;
1348 memcpy(table, data + 13, table_size);
1349
1350 mask = *data;
1351 BUILD_BUG_ON(ARRAY_SIZE(peb2466_ar_ctrl_names) != ARRAY_SIZE(peb2466->ch));
1352 for (i = 0; i < ARRAY_SIZE(peb2466->ch); i++) {
1353 if (!(mask & (1 << i)))
1354 continue;
1355
1356 lookup = &peb2466->ch[i].ar_lookup;
1357 lookup->table = table;
1358 lookup->count = table_size / 4;
1359
1360 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
1361 PEB2466_CR0_AR, 0);
1362 if (ret)
1363 return ret;
1364
1365 ret = peb2466_write_buf(peb2466, PEB2466_AR_FILTER(i),
1366 lookup->table[init_index], 4);
1367 if (ret)
1368 return ret;
1369
1370 ret = regmap_update_bits(peb2466->regmap, PEB2466_CR0(i),
1371 PEB2466_CR0_AR, PEB2466_CR0_AR);
1372 if (ret)
1373 return ret;
1374
1375 lkup_ctrl = &peb2466->ch[i].ar_lkup_ctrl;
1376 lkup_ctrl->lookup = lookup;
1377 lkup_ctrl->reg = PEB2466_AR_FILTER(i);
1378 lkup_ctrl->index = init_index;
1379
1380 ret = peb2466_add_lkup_ctrl(component, lkup_ctrl,
1381 peb2466_ar_ctrl_names[i],
1382 min_val, step);
1383 if (ret)
1384 return ret;
1385 }
1386 return 0;
1387 }
1388
1389 struct peb2466_fw_tag_def {
1390 u16 tag;
1391 u32 lng_min;
1392 u32 lng_max;
1393 int (*parse)(struct snd_soc_component *component,
1394 u16 tag, u32 lng, const u8 *data);
1395 };
1396
1397 #define PEB2466_TAG_DEF_LNG_EQ(__tag, __lng, __parse) { \
1398 .tag = __tag, \
1399 .lng_min = __lng, \
1400 .lng_max = __lng, \
1401 .parse = __parse, \
1402 }
1403
1404 #define PEB2466_TAG_DEF_LNG_MIN(__tag, __lng_min, __parse) { \
1405 .tag = __tag, \
1406 .lng_min = __lng_min, \
1407 .lng_max = U32_MAX, \
1408 .parse = __parse, \
1409 }
1410
1411 static const struct peb2466_fw_tag_def peb2466_fw_tag_defs[] = {
1412 /* TH FILTER */
1413 PEB2466_TAG_DEF_LNG_EQ(0x0001, 1 + 3 * 8, peb2466_fw_parse_thfilter),
1414 /* IMR1 FILTER */
1415 PEB2466_TAG_DEF_LNG_EQ(0x0002, 1 + 2 * 8, peb2466_fw_parse_imr1filter),
1416 /* FRX FILTER */
1417 PEB2466_TAG_DEF_LNG_EQ(0x0003, 1 + 8, peb2466_fw_parse_frxfilter),
1418 /* FRR FILTER */
1419 PEB2466_TAG_DEF_LNG_EQ(0x0004, 1 + 8, peb2466_fw_parse_frrfilter),
1420 /* AX FILTER */
1421 PEB2466_TAG_DEF_LNG_EQ(0x0005, 1 + 4, peb2466_fw_parse_axfilter),
1422 /* AR FILTER */
1423 PEB2466_TAG_DEF_LNG_EQ(0x0006, 1 + 4, peb2466_fw_parse_arfilter),
1424 /* AX TABLE */
1425 PEB2466_TAG_DEF_LNG_MIN(0x0105, 1 + 3 * 4, peb2466_fw_parse_axtable),
1426 /* AR TABLE */
1427 PEB2466_TAG_DEF_LNG_MIN(0x0106, 1 + 3 * 4, peb2466_fw_parse_artable),
1428 };
1429
peb2466_fw_get_tag_def(u16 tag)1430 static const struct peb2466_fw_tag_def *peb2466_fw_get_tag_def(u16 tag)
1431 {
1432 int i;
1433
1434 for (i = 0; i < ARRAY_SIZE(peb2466_fw_tag_defs); i++) {
1435 if (peb2466_fw_tag_defs[i].tag == tag)
1436 return &peb2466_fw_tag_defs[i];
1437 }
1438 return NULL;
1439 }
1440
peb2466_fw_parse(struct snd_soc_component * component,const u8 * data,size_t size)1441 static int peb2466_fw_parse(struct snd_soc_component *component,
1442 const u8 *data, size_t size)
1443 {
1444 const struct peb2466_fw_tag_def *tag_def;
1445 size_t left;
1446 const u8 *buf;
1447 u16 val16;
1448 u16 tag;
1449 u32 lng;
1450 int ret;
1451
1452 /*
1453 * Coefficients firmware binary structure (16bits and 32bits are
1454 * big-endian values).
1455 *
1456 * @0, 16bits: Magic (0x2466)
1457 * @2, 16bits: Version (0x0100 for version 1.0)
1458 * @4, 2+4+N bytes: TLV block
1459 * @4+(2+4+N) bytes: Next TLV block
1460 * ...
1461 *
1462 * Detail of a TLV block:
1463 * @0, 16bits: Tag
1464 * @2, 32bits: Lng
1465 * @6, lng bytes: Data
1466 *
1467 * The detail the Data for a given TLV Tag is provided in the related
1468 * parser.
1469 */
1470
1471 left = size;
1472 buf = data;
1473
1474 if (left < 4) {
1475 dev_err(component->dev, "fw size %zu, exp at least 4\n", left);
1476 return -EINVAL;
1477 }
1478
1479 /* Check magic */
1480 val16 = get_unaligned_be16(buf);
1481 if (val16 != 0x2466) {
1482 dev_err(component->dev, "fw magic 0x%04x exp 0x2466\n", val16);
1483 return -EINVAL;
1484 }
1485 buf += 2;
1486 left -= 2;
1487
1488 /* Check version */
1489 val16 = get_unaligned_be16(buf);
1490 if (val16 != 0x0100) {
1491 dev_err(component->dev, "fw magic 0x%04x exp 0x0100\n", val16);
1492 return -EINVAL;
1493 }
1494 buf += 2;
1495 left -= 2;
1496
1497 while (left) {
1498 if (left < 6) {
1499 dev_err(component->dev, "fw %td/%zu left %zu, exp at least 6\n",
1500 buf - data, size, left);
1501 return -EINVAL;
1502 }
1503 /* Check tag and lng */
1504 tag = get_unaligned_be16(buf);
1505 lng = get_unaligned_be32(buf + 2);
1506 tag_def = peb2466_fw_get_tag_def(tag);
1507 if (!tag_def) {
1508 dev_err(component->dev, "fw %td/%zu tag 0x%04x unknown\n",
1509 buf - data, size, tag);
1510 return -EINVAL;
1511 }
1512 if (lng < tag_def->lng_min || lng > tag_def->lng_max) {
1513 dev_err(component->dev, "fw %td/%zu tag 0x%04x lng %u, exp [%u;%u]\n",
1514 buf - data, size, tag, lng, tag_def->lng_min, tag_def->lng_max);
1515 return -EINVAL;
1516 }
1517 buf += 6;
1518 left -= 6;
1519 if (left < lng) {
1520 dev_err(component->dev, "fw %td/%zu tag 0x%04x lng %u, left %zu\n",
1521 buf - data, size, tag, lng, left);
1522 return -EINVAL;
1523 }
1524
1525 /* TLV block is valid -> parse the data part */
1526 ret = tag_def->parse(component, tag, lng, buf);
1527 if (ret) {
1528 dev_err(component->dev, "fw %td/%zu tag 0x%04x lng %u parse failed\n",
1529 buf - data, size, tag, lng);
1530 return ret;
1531 }
1532
1533 buf += lng;
1534 left -= lng;
1535 }
1536 return 0;
1537 }
1538
peb2466_load_coeffs(struct snd_soc_component * component,const char * fw_name)1539 static int peb2466_load_coeffs(struct snd_soc_component *component, const char *fw_name)
1540 {
1541 const struct firmware *fw;
1542 int ret;
1543
1544 ret = request_firmware(&fw, fw_name, component->dev);
1545 if (ret)
1546 return ret;
1547
1548 ret = peb2466_fw_parse(component, fw->data, fw->size);
1549 release_firmware(fw);
1550
1551 return ret;
1552 }
1553
peb2466_component_probe(struct snd_soc_component * component)1554 static int peb2466_component_probe(struct snd_soc_component *component)
1555 {
1556 struct peb2466 *peb2466 = snd_soc_component_get_drvdata(component);
1557 const char *firmware_name;
1558 int ret;
1559
1560 /* reset peb2466 audio part */
1561 ret = peb2466_reset_audio(peb2466);
1562 if (ret)
1563 return ret;
1564
1565 ret = of_property_read_string(peb2466->spi->dev.of_node,
1566 "firmware-name", &firmware_name);
1567 if (ret)
1568 return (ret == -EINVAL) ? 0 : ret;
1569
1570 return peb2466_load_coeffs(component, firmware_name);
1571 }
1572
1573 static const struct snd_soc_component_driver peb2466_component_driver = {
1574 .probe = peb2466_component_probe,
1575 .controls = peb2466_controls,
1576 .num_controls = ARRAY_SIZE(peb2466_controls),
1577 .dapm_widgets = peb2466_dapm_widgets,
1578 .num_dapm_widgets = ARRAY_SIZE(peb2466_dapm_widgets),
1579 .dapm_routes = peb2466_dapm_routes,
1580 .num_dapm_routes = ARRAY_SIZE(peb2466_dapm_routes),
1581 .endianness = 1,
1582 };
1583
1584 /*
1585 * The mapping used for the relationship between the gpio offset and the
1586 * physical pin is the following:
1587 *
1588 * offset pin
1589 * 0 SI1_0
1590 * 1 SI1_1
1591 * 2 SI2_0
1592 * 3 SI2_1
1593 * 4 SI3_0
1594 * 5 SI3_1
1595 * 6 SI4_0
1596 * 7 SI4_1
1597 * 8 SO1_0
1598 * 9 SO1_1
1599 * 10 SO2_0
1600 * 11 SO2_1
1601 * 12 SO3_0
1602 * 13 SO3_1
1603 * 14 SO4_0
1604 * 15 SO4_1
1605 * 16 SB1_0
1606 * 17 SB1_1
1607 * 18 SB2_0
1608 * 19 SB2_1
1609 * 20 SB3_0
1610 * 21 SB3_1
1611 * 22 SB4_0
1612 * 23 SB4_1
1613 * 24 SB1_2
1614 * 25 SB2_2
1615 * 26 SB3_2
1616 * 27 SB4_2
1617 */
1618
peb2466_chip_gpio_offset_to_data_regmask(unsigned int offset,unsigned int * xr_reg,unsigned int * mask)1619 static int peb2466_chip_gpio_offset_to_data_regmask(unsigned int offset,
1620 unsigned int *xr_reg,
1621 unsigned int *mask)
1622 {
1623 if (offset < 16) {
1624 /*
1625 * SIx_{0,1} and SOx_{0,1}
1626 * Read accesses read SIx_{0,1} values
1627 * Write accesses write SOx_{0,1} values
1628 */
1629 *xr_reg = PEB2466_XR0;
1630 *mask = (1 << (offset % 8));
1631 return 0;
1632 }
1633 if (offset < 24) {
1634 /* SBx_{0,1} */
1635 *xr_reg = PEB2466_XR1;
1636 *mask = (1 << (offset - 16));
1637 return 0;
1638 }
1639 if (offset < 28) {
1640 /* SBx_2 */
1641 *xr_reg = PEB2466_XR3;
1642 *mask = (1 << (offset - 24 + 4));
1643 return 0;
1644 }
1645 return -EINVAL;
1646 }
1647
peb2466_chip_gpio_offset_to_dir_regmask(unsigned int offset,unsigned int * xr_reg,unsigned int * mask)1648 static int peb2466_chip_gpio_offset_to_dir_regmask(unsigned int offset,
1649 unsigned int *xr_reg,
1650 unsigned int *mask)
1651 {
1652 if (offset < 16) {
1653 /* Direction cannot be changed for these GPIOs */
1654 return -EINVAL;
1655 }
1656 if (offset < 24) {
1657 *xr_reg = PEB2466_XR2;
1658 *mask = (1 << (offset - 16));
1659 return 0;
1660 }
1661 if (offset < 28) {
1662 *xr_reg = PEB2466_XR3;
1663 *mask = (1 << (offset - 24));
1664 return 0;
1665 }
1666 return -EINVAL;
1667 }
1668
peb2466_chip_gpio_get_cache(struct peb2466 * peb2466,unsigned int xr_reg)1669 static unsigned int *peb2466_chip_gpio_get_cache(struct peb2466 *peb2466,
1670 unsigned int xr_reg)
1671 {
1672 unsigned int *cache;
1673
1674 switch (xr_reg) {
1675 case PEB2466_XR0:
1676 cache = &peb2466->gpio.cache.xr0;
1677 break;
1678 case PEB2466_XR1:
1679 cache = &peb2466->gpio.cache.xr1;
1680 break;
1681 case PEB2466_XR2:
1682 cache = &peb2466->gpio.cache.xr2;
1683 break;
1684 case PEB2466_XR3:
1685 cache = &peb2466->gpio.cache.xr3;
1686 break;
1687 default:
1688 cache = NULL;
1689 break;
1690 }
1691 return cache;
1692 }
1693
peb2466_chip_gpio_update_bits(struct peb2466 * peb2466,unsigned int xr_reg,unsigned int mask,unsigned int val)1694 static int peb2466_chip_gpio_update_bits(struct peb2466 *peb2466, unsigned int xr_reg,
1695 unsigned int mask, unsigned int val)
1696 {
1697 unsigned int tmp;
1698 unsigned int *cache;
1699 int ret;
1700
1701 /*
1702 * Read and write accesses use different peb2466 internal signals (input
1703 * signals on reads and output signals on writes). regmap_update_bits
1704 * cannot be used to read/modify/write the value.
1705 * So, a specific cache value is used.
1706 */
1707
1708 mutex_lock(&peb2466->gpio.lock);
1709
1710 cache = peb2466_chip_gpio_get_cache(peb2466, xr_reg);
1711 if (!cache) {
1712 ret = -EINVAL;
1713 goto end;
1714 }
1715
1716 tmp = *cache;
1717 tmp &= ~mask;
1718 tmp |= val;
1719
1720 ret = regmap_write(peb2466->regmap, xr_reg, tmp);
1721 if (ret)
1722 goto end;
1723
1724 *cache = tmp;
1725 ret = 0;
1726
1727 end:
1728 mutex_unlock(&peb2466->gpio.lock);
1729 return ret;
1730 }
1731
peb2466_chip_gpio_set(struct gpio_chip * c,unsigned int offset,int val)1732 static int peb2466_chip_gpio_set(struct gpio_chip *c, unsigned int offset,
1733 int val)
1734 {
1735 struct peb2466 *peb2466 = gpiochip_get_data(c);
1736 unsigned int xr_reg;
1737 unsigned int mask;
1738 int ret;
1739
1740 if (offset < 8) {
1741 /*
1742 * SIx_{0,1} signals cannot be set and writing the related
1743 * register will change the SOx_{0,1} signals
1744 */
1745 dev_warn(&peb2466->spi->dev, "cannot set gpio %d (read-only)\n",
1746 offset);
1747 return -EINVAL;
1748 }
1749
1750 ret = peb2466_chip_gpio_offset_to_data_regmask(offset, &xr_reg, &mask);
1751 if (ret) {
1752 dev_err(&peb2466->spi->dev, "cannot set gpio %d (%d)\n",
1753 offset, ret);
1754 return ret;
1755 }
1756
1757 ret = peb2466_chip_gpio_update_bits(peb2466, xr_reg, mask, val ? mask : 0);
1758 if (ret) {
1759 dev_err(&peb2466->spi->dev, "set gpio %d (0x%x, 0x%x) failed (%d)\n",
1760 offset, xr_reg, mask, ret);
1761 }
1762
1763 return ret;
1764 }
1765
peb2466_chip_gpio_get(struct gpio_chip * c,unsigned int offset)1766 static int peb2466_chip_gpio_get(struct gpio_chip *c, unsigned int offset)
1767 {
1768 struct peb2466 *peb2466 = gpiochip_get_data(c);
1769 bool use_cache = false;
1770 unsigned int *cache;
1771 unsigned int xr_reg;
1772 unsigned int mask;
1773 unsigned int val;
1774 int ret;
1775
1776 if (offset >= 8 && offset < 16) {
1777 /*
1778 * SOx_{0,1} signals cannot be read. Reading the related
1779 * register will read the SIx_{0,1} signals.
1780 * Use the cache to get value;
1781 */
1782 use_cache = true;
1783 }
1784
1785 ret = peb2466_chip_gpio_offset_to_data_regmask(offset, &xr_reg, &mask);
1786 if (ret) {
1787 dev_err(&peb2466->spi->dev, "cannot get gpio %d (%d)\n",
1788 offset, ret);
1789 return -EINVAL;
1790 }
1791
1792 if (use_cache) {
1793 cache = peb2466_chip_gpio_get_cache(peb2466, xr_reg);
1794 if (!cache)
1795 return -EINVAL;
1796 val = *cache;
1797 } else {
1798 ret = regmap_read(peb2466->regmap, xr_reg, &val);
1799 if (ret) {
1800 dev_err(&peb2466->spi->dev, "get gpio %d (0x%x, 0x%x) failed (%d)\n",
1801 offset, xr_reg, mask, ret);
1802 return ret;
1803 }
1804 }
1805
1806 return !!(val & mask);
1807 }
1808
peb2466_chip_get_direction(struct gpio_chip * c,unsigned int offset)1809 static int peb2466_chip_get_direction(struct gpio_chip *c, unsigned int offset)
1810 {
1811 struct peb2466 *peb2466 = gpiochip_get_data(c);
1812 unsigned int xr_reg;
1813 unsigned int mask;
1814 unsigned int val;
1815 int ret;
1816
1817 if (offset < 8) {
1818 /* SIx_{0,1} */
1819 return GPIO_LINE_DIRECTION_IN;
1820 }
1821 if (offset < 16) {
1822 /* SOx_{0,1} */
1823 return GPIO_LINE_DIRECTION_OUT;
1824 }
1825
1826 ret = peb2466_chip_gpio_offset_to_dir_regmask(offset, &xr_reg, &mask);
1827 if (ret) {
1828 dev_err(&peb2466->spi->dev, "cannot get gpio %d direction (%d)\n",
1829 offset, ret);
1830 return ret;
1831 }
1832
1833 ret = regmap_read(peb2466->regmap, xr_reg, &val);
1834 if (ret) {
1835 dev_err(&peb2466->spi->dev, "get dir gpio %d (0x%x, 0x%x) failed (%d)\n",
1836 offset, xr_reg, mask, ret);
1837 return ret;
1838 }
1839
1840 return val & mask ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1841 }
1842
peb2466_chip_direction_input(struct gpio_chip * c,unsigned int offset)1843 static int peb2466_chip_direction_input(struct gpio_chip *c, unsigned int offset)
1844 {
1845 struct peb2466 *peb2466 = gpiochip_get_data(c);
1846 unsigned int xr_reg;
1847 unsigned int mask;
1848 int ret;
1849
1850 if (offset < 8) {
1851 /* SIx_{0,1} */
1852 return 0;
1853 }
1854 if (offset < 16) {
1855 /* SOx_{0,1} */
1856 return -EINVAL;
1857 }
1858
1859 ret = peb2466_chip_gpio_offset_to_dir_regmask(offset, &xr_reg, &mask);
1860 if (ret) {
1861 dev_err(&peb2466->spi->dev, "cannot set gpio %d direction (%d)\n",
1862 offset, ret);
1863 return ret;
1864 }
1865
1866 ret = peb2466_chip_gpio_update_bits(peb2466, xr_reg, mask, 0);
1867 if (ret) {
1868 dev_err(&peb2466->spi->dev, "Set dir in gpio %d (0x%x, 0x%x) failed (%d)\n",
1869 offset, xr_reg, mask, ret);
1870 return ret;
1871 }
1872
1873 return 0;
1874 }
1875
peb2466_chip_direction_output(struct gpio_chip * c,unsigned int offset,int val)1876 static int peb2466_chip_direction_output(struct gpio_chip *c, unsigned int offset, int val)
1877 {
1878 struct peb2466 *peb2466 = gpiochip_get_data(c);
1879 unsigned int xr_reg;
1880 unsigned int mask;
1881 int ret;
1882
1883 if (offset < 8) {
1884 /* SIx_{0,1} */
1885 return -EINVAL;
1886 }
1887
1888 ret = peb2466_chip_gpio_set(c, offset, val);
1889 if (ret)
1890 return ret;
1891
1892 if (offset < 16) {
1893 /* SOx_{0,1} */
1894 return 0;
1895 }
1896
1897 ret = peb2466_chip_gpio_offset_to_dir_regmask(offset, &xr_reg, &mask);
1898 if (ret) {
1899 dev_err(&peb2466->spi->dev, "cannot set gpio %d direction (%d)\n",
1900 offset, ret);
1901 return ret;
1902 }
1903
1904 ret = peb2466_chip_gpio_update_bits(peb2466, xr_reg, mask, mask);
1905 if (ret) {
1906 dev_err(&peb2466->spi->dev, "Set dir in gpio %d (0x%x, 0x%x) failed (%d)\n",
1907 offset, xr_reg, mask, ret);
1908 return ret;
1909 }
1910
1911 return 0;
1912 }
1913
peb2466_reset_gpio(struct peb2466 * peb2466)1914 static int peb2466_reset_gpio(struct peb2466 *peb2466)
1915 {
1916 static const struct reg_sequence reg_reset[] = {
1917 /* Output pins at 0, input/output pins as input */
1918 { .reg = PEB2466_XR0, .def = 0 },
1919 { .reg = PEB2466_XR1, .def = 0 },
1920 { .reg = PEB2466_XR2, .def = 0 },
1921 { .reg = PEB2466_XR3, .def = 0 },
1922 };
1923
1924 peb2466->gpio.cache.xr0 = 0;
1925 peb2466->gpio.cache.xr1 = 0;
1926 peb2466->gpio.cache.xr2 = 0;
1927 peb2466->gpio.cache.xr3 = 0;
1928
1929 return regmap_multi_reg_write(peb2466->regmap, reg_reset, ARRAY_SIZE(reg_reset));
1930 }
1931
peb2466_gpio_init(struct peb2466 * peb2466)1932 static int peb2466_gpio_init(struct peb2466 *peb2466)
1933 {
1934 int ret;
1935
1936 mutex_init(&peb2466->gpio.lock);
1937
1938 ret = peb2466_reset_gpio(peb2466);
1939 if (ret)
1940 return ret;
1941
1942 peb2466->gpio.gpio_chip.owner = THIS_MODULE;
1943 peb2466->gpio.gpio_chip.label = dev_name(&peb2466->spi->dev);
1944 peb2466->gpio.gpio_chip.parent = &peb2466->spi->dev;
1945 peb2466->gpio.gpio_chip.base = -1;
1946 peb2466->gpio.gpio_chip.ngpio = 28;
1947 peb2466->gpio.gpio_chip.get_direction = peb2466_chip_get_direction;
1948 peb2466->gpio.gpio_chip.direction_input = peb2466_chip_direction_input;
1949 peb2466->gpio.gpio_chip.direction_output = peb2466_chip_direction_output;
1950 peb2466->gpio.gpio_chip.get = peb2466_chip_gpio_get;
1951 peb2466->gpio.gpio_chip.set = peb2466_chip_gpio_set;
1952 peb2466->gpio.gpio_chip.can_sleep = true;
1953
1954 return devm_gpiochip_add_data(&peb2466->spi->dev, &peb2466->gpio.gpio_chip,
1955 peb2466);
1956 }
1957
peb2466_spi_probe(struct spi_device * spi)1958 static int peb2466_spi_probe(struct spi_device *spi)
1959 {
1960 struct peb2466 *peb2466;
1961 unsigned long mclk_rate;
1962 int ret;
1963 u8 xr5;
1964
1965 spi->bits_per_word = 8;
1966 ret = spi_setup(spi);
1967 if (ret < 0)
1968 return ret;
1969
1970 peb2466 = devm_kzalloc(&spi->dev, sizeof(*peb2466), GFP_KERNEL);
1971 if (!peb2466)
1972 return -ENOMEM;
1973
1974 peb2466->spi = spi;
1975
1976 peb2466->regmap = devm_regmap_init(&peb2466->spi->dev, NULL, peb2466,
1977 &peb2466_regmap_config);
1978 if (IS_ERR(peb2466->regmap))
1979 return PTR_ERR(peb2466->regmap);
1980
1981 peb2466->reset_gpio = devm_gpiod_get_optional(&peb2466->spi->dev,
1982 "reset", GPIOD_OUT_LOW);
1983 if (IS_ERR(peb2466->reset_gpio))
1984 return PTR_ERR(peb2466->reset_gpio);
1985
1986 peb2466->mclk = devm_clk_get_enabled(&peb2466->spi->dev, "mclk");
1987 if (IS_ERR(peb2466->mclk))
1988 return PTR_ERR(peb2466->mclk);
1989
1990 if (peb2466->reset_gpio) {
1991 gpiod_set_value_cansleep(peb2466->reset_gpio, 1);
1992 udelay(4);
1993 gpiod_set_value_cansleep(peb2466->reset_gpio, 0);
1994 udelay(4);
1995 }
1996
1997 spi_set_drvdata(spi, peb2466);
1998
1999 mclk_rate = clk_get_rate(peb2466->mclk);
2000 switch (mclk_rate) {
2001 case 1536000:
2002 xr5 = PEB2466_XR5_MCLK_1536;
2003 break;
2004 case 2048000:
2005 xr5 = PEB2466_XR5_MCLK_2048;
2006 break;
2007 case 4096000:
2008 xr5 = PEB2466_XR5_MCLK_4096;
2009 break;
2010 case 8192000:
2011 xr5 = PEB2466_XR5_MCLK_8192;
2012 break;
2013 default:
2014 dev_err(&peb2466->spi->dev, "Unsupported clock rate %lu\n",
2015 mclk_rate);
2016 ret = -EINVAL;
2017 goto failed;
2018 }
2019 ret = regmap_write(peb2466->regmap, PEB2466_XR5, xr5);
2020 if (ret) {
2021 dev_err(&peb2466->spi->dev, "Setting MCLK failed (%d)\n", ret);
2022 goto failed;
2023 }
2024
2025 ret = devm_snd_soc_register_component(&spi->dev, &peb2466_component_driver,
2026 &peb2466_dai_driver, 1);
2027 if (ret)
2028 goto failed;
2029
2030 if (IS_ENABLED(CONFIG_GPIOLIB)) {
2031 ret = peb2466_gpio_init(peb2466);
2032 if (ret)
2033 goto failed;
2034 }
2035
2036 return 0;
2037
2038 failed:
2039 return ret;
2040 }
2041
2042 static const struct of_device_id peb2466_of_match[] = {
2043 { .compatible = "infineon,peb2466", },
2044 { }
2045 };
2046 MODULE_DEVICE_TABLE(of, peb2466_of_match);
2047
2048 static const struct spi_device_id peb2466_id_table[] = {
2049 { "peb2466", 0 },
2050 { }
2051 };
2052 MODULE_DEVICE_TABLE(spi, peb2466_id_table);
2053
2054 static struct spi_driver peb2466_spi_driver = {
2055 .driver = {
2056 .name = "peb2466",
2057 .of_match_table = peb2466_of_match,
2058 },
2059 .id_table = peb2466_id_table,
2060 .probe = peb2466_spi_probe,
2061 };
2062
2063 module_spi_driver(peb2466_spi_driver);
2064
2065 MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
2066 MODULE_DESCRIPTION("PEB2466 ALSA SoC driver");
2067 MODULE_LICENSE("GPL");
2068