xref: /petsc/config/BuildSystem/config/atomics.py (revision dcca6d9d80ebd869fe6029bd05a3aa9faafef49e)
1import config.base
2
3import os
4
5class Configure(config.base.Configure):
6  def __init__(self, framework):
7    config.base.Configure.__init__(self, framework)
8    self.headerPrefix = 'PETSC'
9    return
10
11  def setupDependencies(self, framework):
12    config.base.Configure.setupDependencies(self, framework)
13    self.setCompilers = framework.require('config.setCompilers', self)
14    self.libraries    = framework.require('config.libraries', self)
15    return
16
17  def configureCPURelax(self):
18    ''' Definitions for cpu relax assembly instructions '''
19    # Definition for cpu_relax()
20    # From Linux documentation
21    # cpu_relax() call can lower power consumption or yield to a hyperthreaded
22    # twin processor; it also happens to serve as a compiler barrier
23
24    # x86
25    if self.checkCompile('', 'asm volatile("rep; nop" ::: "memory");'):
26      self.addDefine('CPU_RELAX()','asm volatile("rep; nop" ::: "memory")')
27      return
28    # PowerPC
29    if self.checkCompile('','do { HMT_low; HMT_medium; __asm__ __volatile__ ("":::"memory"); } while (0)'):
30      self.addDefine('CPU_RELAX()','do { HMT_low; HMT_medium; __asm__ __volatile__ ("":::"memory"); } while (0)')
31      return
32    elif self.checkCompile('','__asm__ __volatile__ ("":::"memory");'):
33      self.addDefine('CPU_RELAX()','__asm__ __volatile__ ("":::"memory")')
34      return
35
36  def configureMemoryBarriers(self):
37    ''' Definitions for memory barrier instructions'''
38    # ---- Definitions for x86_64 -----
39    # General Memory Barrier
40    if self.checkCompile('','asm volatile("mfence":::"memory")'):
41      self.addDefine('MEMORY_BARRIER()','asm volatile("mfence":::"memory")')
42    # Read Memory Barrier
43    if self.checkCompile('','asm volatile("lfence":::"memory")'):
44      self.addDefine('READ_MEMORY_BARRIER()','asm volatile("lfence":::"memory")')
45    # Write Memory Barrier
46    if self.checkCompile('','asm volatile("sfence":::"memory")'):
47      self.addDefine('WRITE_MEMORY_BARRIER()','asm volatile("sfence":::"memory")')
48    return
49
50  def configure(self):
51    self.executeTest(self.configureCPURelax)
52    self.executeTest(self.configureMemoryBarriers)
53    return
54